SEMICONDUCTOR DEVICES CONTAINING TRENCH MOSFETS WITH SUPERJUNCTIONS

• US 20110198689A1
• Filed: 02/17/2010
• Published: 08/18/2011
• Est. Priority Date: 02/17/2010
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kim, Suku
• Application Number:
  US12/707,323
• Publication Number:
  US 20110198689A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor devices combining a MOSFET architecture with a PN super-junction structure and methods for making such devices are described. The MOSFET architecture can be made using a trench configuration containing a gate that is sandwiched between thick dielectric layers in the top and the bottom of the trench. The PN junction of the super-junction structure is formed between n-type dopant regions in the sidewalls of the trench and a p-type epitaxial layer. The gate of the trench MOSFET is separated from the super-junction structure using a gate insulating layer. Such semiconductor devices can have a lower capacitance and a higher breakdown voltage relative to shield-based trench MOSFET devices and can replace such devices in medium to high voltage ranges. Other embodiments are described.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate heavily doped with a dopant of a first conductivity type;

an epitaxial layer on the substrate, the epitaxial layer being lightly doped with a dopant of a second conductivity type;

a trench formed in the epitaxial layer, the trench containing a MOSFET structure without a shield electrode and also containing a sidewall that is lightly doped with a dopant of a first conductivity type;

a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure; and

a drain contacting a bottom portion of the substrate.

2. The device of claim 1, wherein the first conductivity type dopant is an n-type dopant and the second conductivity type dopant is a p-type dopant.

3. The device of claim 1, wherein the epitaxial layer contains a concentration gradient that has a higher concentration at an upper surface and a lower concentration near the substrate.

4. The device of claim 3, wherein the concentration gradient decreases from the upper surface to the substrate in a substantially uniform or substantially step-wise manner.

5. The device of claim 1, wherein the MOSFET structure comprises a gate vertically insulated within the trench by deposited insulating materials.

6. The device of claim 5, wherein the gate is insulated from the epitaxial layer by a gate insulating layer.

7. The device of claim 1, wherein the trench comprises a sidewall with an angle range from about 90 to about 70 degrees.

8. The device of claim 1, wherein the trench sidewall dopant has been implanted at an angle ranging from more than 0, which is perpendicular to the surface of the substrate, to about 40 degrees.

9. A semiconductor device, comprising:

a semiconductor substrate heavily doped with a dopant of a first conductivity type;

an epitaxial layer on the substrate, the epitaxial layer being lightly doped with a dopant of a second conductivity type;

a trench formed in the epitaxial layer, the trench containing a sidewall that is lightly doped with a dopant of a first conductivity type, a gate vertically insulated within the trench by a bottom oxide region and an insulation cap and herein the gate is insulated from the epitaxial layer by a gate insulating layer;

a source layer contacting an upper surface of the epitaxial layer and an upper surface of the insulation cap; and

a drain contacting a bottom portion of the substrate.

10. The device of claim 9, wherein the first conductivity type dopant is an n-type dopant and the second conductivity type dopant is a p-type dopant.

11. The device of claim 9, wherein epitaxial layer contains a concentration gradient with a higher concentration at an upper surface and a lower concentration near the substrate.

12. The device of claim 11, wherein the concentration gradient decreases from the upper surface to the substrate in a substantially uniform or substantially step-wise manner.

13. The device of claim 9, wherein the trench comprises a sidewall with an angle range from about 90 to about 70 degrees.

14. The device of claim 9, wherein the trench sidewall dopant has been implanted at an angle ranging from more than 0 to about 40 degrees.

15. An electronic apparatus containing a semiconductor device, comprising:

a semiconductor substrate heavily doped with a dopant of a first conductivity type;

an epitaxial layer on the substrate, the epitaxial layer being lightly doped with a dopant of a second conductivity type;

a trench formed in the epitaxial layer, the trench containing a sidewall that is lightly doped with a dopant of a first conductivity type, a gate vertically insulated within the trench by a bottom oxide region and an insulation cap and herein the gate is insulated from the epitaxial layer by a gate insulating layer;

a source layer contacting an upper surface of the epitaxial layer and an upper surface of the insulation cap; and

a drain contacting a bottom portion of the substrate.

16. The apparatus of claim 15, wherein the first conductivity type dopant is an n-type dopant and the second conductivity type dopant is a p-type dopant.

17. The apparatus of claim 15, wherein the epitaxial layer contains a concentration gradient with a higher concentration at an upper surface and a lower concentration near the substrate.

18. The apparatus of claim 17, wherein the concentration gradient decreases from the upper surface to the substrate in a substantially uniform or substantially step-wise manner.

19. The apparatus of claim 15, wherein the trench comprises a sidewall with an angle range from about 90 to about 70 degrees.

20. The apparatus of claim 15, wherein the trench sidewall dopant has been implanted at an angle ranging from more than 0 to about 40 degrees.

21. The apparatus of claim 15, further comprising another epitaxial layer doped with a first conductivity type located between the substrate and the epitaxial layer.