METHOD FOR THINNING A WAFER

• US 20110198721A1
• Filed: 02/12/2010
• Published: 08/18/2011
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chia-Lin, Wu, Weng-Jin, Shih, Chu-Sung, Hsu, Fu-Chi, YANG, Ku-Feng, Lu, Hsin-Hsien, Shue, Shau-Lin
• Granted Patent: US 8,252,682 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body

Abstract

A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

Claims

1. A method for thinning a wafer, comprising:

providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of device structures, each of the device structures being substantially sealed by a liner layer and a barrier layer;

providing a wafer carrier, wherein the wafer carrier is attached to the second side of the wafer;

thinning the first side of the wafer to a predetermined thickness;

recessing the first side of the wafer to partially expose top portions of the liner layer, barrier layer, and the device structures;

depositing an isolation layer over the first side of the wafer and the top portions of the liner layer, barrier layer, and the device structures;

depositing an insulation layer over the isolation layer;

planarizing the insulation layer to expose top portions of the device structures for electrical connection; and

depositing a dielectric layer over the planarized first side of the wafer.

2. The method of claim 1, wherein the set of device structures comprises one or more of a through silicon via (TSV), a trench, or an alignment mark.

3. The method of claim 1, wherein the liner layer is formed by chemical vapor deposition (CVD) or spin-on glass (SOG), and wherein further the liner layer has a thickness range of from about 1,000 Angstroms to about 2,000 Angstroms.

4. The method of claim 1, wherein the barrier layer comprises tantalum (Ta), Ta/TaN, titanium (Ti), or Ti/Ti, and has a thickness range of from about 50 Angstroms to about 500 Angstroms.

5. The method of claim 1, wherein the wafer carrier is attached to the second side of the wafer by a method selected from the group consisting of adhesive bonding, adhesive tape, tape bonding, and resin bonding.

6. The method of claim 1, wherein thinning the wafer comprises mechanically thinning the wafer using grinding or chemical mechanical polish (CMP).

7. The method of claim 1, wherein the step of recessing comprises wet etching, dry etching, dry polishing, or plasma etching.

8. The method of claim 1, wherein the isolation layer has a thickness range of from about 100 Angstroms to about 1,000 Angstroms.

9. The method of claim 1, wherein the isolation layer is formed by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or spin-on coating.

10. The method of claim 1, wherein the isolation layer comprises SiN_X, SiON_X, SiO_X, TaN, TiN, carbides, SOG, BCB, polyimide, TEOS, or polymers.

11. The method of claim 1, wherein the insulation layer has a thickness of from about 2,000 Angstroms to about 20,000 Angstroms and comprises an oxide, a high-k dielectric material, or polyimide.

12. The method of claim 1, further comprising forming redistribution layer (RDLs) in the dielectric layer, the RDLs for electrically coupling to the exposed device structures.

13. A product made by the method of claim 2.

14. A method for thinning a wafer, comprising:

providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs being substantially sealed by a liner layer and a barrier layer;

providing a wafer carrier, wherein the wafer carrier is attached to the second side of the wafer;

thinning the first side of the wafer to a predetermined thickness;

recessing the first side of the wafer to partially expose portions of the liner layer, barrier layer, and the TSVs, the liner layers, the barrier layers and the TSVs protruding from the wafer;

depositing an isolation layer over the first side of the wafer and the top portions of the liner layer, barrier layer, and the TSVs;

depositing an insulation layer over the isolation layer;

planarizing the insulation layer to expose top portions of the TSVs;

depositing a dielectric layer over the planarized first side of the wafer; and

forming one or more electrical contacts for electrical connection to the exposed one or more TSVs.

15. The method of claim 14, wherein the barrier layer comprises tantalum (Ta), Ta/TaN, titanium (Ti), or Ti/Ti.

16. The method of claim 14, wherein the wafer carrier comprises a silicon substrate, glass substrate, polymer substrate, polymer-based composite substrate, or thick tape and the wafer carrier is attached to the second side of the wafer by a method selected from the group consisting of adhesive bonding, adhesive tape, tape bonding, and resin bonding.

17. The method of claim 14, wherein thinning the wafer is performed at least in part by grinding or chemical mechanical polish (CMP), and the step of recessing comprises wet etching, dry etching, or plasma etching.

18. The method of claim 14, wherein the isolation layer has a thickness range of from about 100 Angstroms to about 1,000 Angstroms and is formed by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or spin-on coating.

19. The method of claim 14, wherein the isolation layer comprises SiN_X, SiON_X, SiO_X, TaN, TiN, carbides, SOG, BCB, polyimide, TEOS, or polymers.

20. The method of claim 14, wherein the insulation layer has a thickness of from about 2,000 Angstroms to about 20,000 Angstroms and comprises an oxide, a high-k dielectric material, or polyimide.

21. The method of claim 14, wherein the one or more electrical contacts comprise a redistribution layer (RDL) or metal contact.

22. A semiconductor device, comprising:

a semiconductor wafer having a plurality of semiconductor chips, each of the plurality of chips having a set of device structures embedded therein, each of the device structures having a planarized, partially exposed top portion;

liner layers substantially sealing the sides of the device structures;

barrier layers substantially sealing the sides of the liner layers;

isolation layers formed on the sides of a top portion of the barrier layers, the isolation layers formed between any two of the device structures;

insulation layers formed above the isolation layers, the insulation layers planarized with the planarized top portions of the device structures;

a dielectric layer formed above the planarized insulation layer and the planarized top portions of the device structures; and

a plurality of redistribution layers (RDLs) embedded within the dielectric layer, the RDLs coupled to the planarized, exposed top portions of the device structures.

23. The semiconductor device of claim 22, wherein the set of device structures comprises one or more of a through silicon via (TSV), a trench, or an alignment mark.

24. The semiconductor device of claim 22, wherein each of the liner layers comprises an oxide material and has a thickness in the range of from about 1,000 Angstroms to about 2,000 Angstroms.

25. The semiconductor device of claim 22, wherein each of the barrier layers comprises tantalum (Ta), Ta/TaN, titanium (Ti), or Ti/Ti, and has a thickness in the range of from about 50 Angstroms to about 500 Angstroms.

26. The semiconductor device of claim 22, wherein each of the isolation layers comprises SiN_X, SiON_X, SiO_X, TaN, TiN, carbides, SOG, BCB, polyimide, TEOS, or polymers and has a thickness in the range of from about 100 Angstroms to about 1,000 Angstroms.

27. The semiconductor device of claim 22, wherein each of the insulation layers has a thickness of from about 2,000 Angstroms to about 20,000 Angstroms and comprises an oxide, a high-k dielectric material, or polyimide.