PANELIZED PACKAGING WITH TRANSFERRED DIELECTRIC

• US 20110198762A1
• Filed: 01/05/2011
• Published: 08/18/2011
• Est. Priority Date: 02/16/2010
• Status: Abandoned Application

• Current Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Original Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Inventors: Scanlan, Christopher M.
• Application Number:
  US12/985,212
• Publication Number:
  US 20110198762A1
• Time in Patent Office: Days
• US Class Current: 257/793
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A method of panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die units in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less patterning technique.

Claims

1. A method comprising:

placing a plurality of die units on a surface of a dielectric film;

curing the dielectric film after placing the plurality of die units on the surface of the dielectric film;

encapsulating the plurality of die units on the cured dielectric film with an encapsulant; and

patterning the cured dielectric film to expose each of the plurality of die units utilizing a mask-less patterning technique.

2. The method of claim 1, wherein placing the plurality of die units on the surface of the dielectric film comprises placing the plurality of die units on a surface of a semi-cured dielectric film.

3. The method of claim 2, wherein the semi-cured dielectric film comprises a B-stage cured epoxy.

4. The method of claim 1, wherein the mask-less patterning technique comprises laser ablation.

5. The method of claim 2, wherein encapsulating the plurality of die units on the cured dielectric film comprises compression molding.

6. The method of claim 2, wherein encapsulating the plurality of die units on the cured dielectric film comprises lamination.

7. The method of claim 6, wherein lamination comprises vacuum lamination.

8. The method of claim 7, wherein vacuum lamination comprises:

placing a semi-cured encapsulant film over the plurality of die units on the cured dielectric film; and

applying heat and pressure under vacuum to the semi-cured encapsulant film.

9. The method of claim 1, wherein the plurality of die units are placed on a surface of the dielectric film opposite a second surface which is laminated to a carrier substrate.

10. The method of claim 9, further comprising releasing the carrier substrate from the cured dielectric film after encapsulating the plurality of die units on the cured dielectric film, and prior to patterning the cured dielectric film.

11. The method of claim 1, further comprising:

applying a photoimageable polymer layer over the patterned cured dielectric film; and

forming a plurality of openings in the photoimageable polymer layer using a photolithographic patterning technique.

12. The method of claim 11, further comprising:

cutting through the cured dielectric film and the encapsulant without cutting through the photoimageable polymer layer.

13. The method of claim 1, further comprising:

forming a seed layer on the patterned cured dielectric film;

forming a patterned photoresist layer over the seed layer; and

plating within openings of the patterned photoresist layer and the patterned cured dielectric film to form first level vias within the patterned cured dielectric film and redistribution layer (RDL) traces over the patterned cured dielectric film.

14. The method of claim 13, further comprising:

removing the patterned photoresist layer and a portion of the seed layer under the patterned photoresist layer after plating; and

forming a photoimageable polymer layer over the patterned cured die attached film and RDL traces.

15. The method of claim 14, further comprising:

patterning the photoimageable polymer layer to expose the RDL traces.

16. The method of claim 15, further comprising:

singulating the plurality of die units.

17. A package comprising:

a non-photoimageable dielectric film;

an active surface of a die unit attached to the dielectric film;

a redistribution layer formed over the dielectric film and in electrical communication with the active surface of the die unit; and

an encapsulant layer comprising epoxy encapsulating the die unit on the dielectric film;

wherein the dielectric film and the encapsulant layer both comprise greater than approximately 50% of a ceramic filler, by weight.

18. The package of claim 17, further comprising:

a polymer layer over the dielectric film;

an opening formed in the polymer layer; and

wherein lateral edges of the encapsulant layer and dielectric film are substantially flush.

19. The package of claim 18, wherein the opening formed in the polymer layer exposes a redistribution layer (RDL).

20. The package of claim 19, wherein the dielectric film and encapsulant layer both have a Tg greater than or equal to 190°

C.