METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20110199116A1
• Filed: 02/16/2010
• Published: 08/18/2011
• Est. Priority Date: 02/16/2010
• Status: Abandoned Application

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: NuPGA Corporation
• Inventors: Beinglass, Israel, Cronquist, Brian, de Jong, J. L., Or-Bach, Zvi, Wurman, Zeev
• Application Number:
  US12/706,520
• Publication Number:
  US 20110199116A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.

Claims

1. A Configurable device comprising:

a logic die connected by at least one through silicon-via (TSV) to a die comprising input/output cell.

2. A Configurable device according to claim 1 wherein said logic die has a plurality of potential dice lines.

3. A Configurable device according to claim 1 wherein said logic die comprises at least two micro control units (MCUs) and wherein said MCUs are interconnected by at least one fixed connection.

4. A Configurable device according to claim 1 wherein said I/O die is fabricated in a process older than said logic die.

5. A semiconductor device comprising:

a first single crystal silicon layer;

at least one metal layer comprising copper overlying said first single crystal silicon layer; and

a second thin single crystal silicon layer of less than 1 micron thickness overlying said at least one metal layer;

wherein said second thin single crystal silicon layer comprises a plurality of transistors with source and drain in one sub-layer of said second thin crystal silicon layer.

12. A semiconductor device according to claim 5 wherein said transistors are aligned to said metal layers within 200 nm.

13. A semiconductor device according to claim 5 wherein said second transistors are defined by a process comprising a step of etching.

14. A semiconductor device according to claim 13 and wherein said process further comprises a step of optical annealing.

6. A semiconductor device comprising:

a first single crystal silicon layer having a plurality of first transistors and at least one metal layer comprising copper on top of said first transistors forming device circuitry;

a second thin single crystal silicon layer of less than 1 micron thickness overlying said multiple metal layers, wherein said second thin single crystal silicon layer has a plurality of second transistors comprising N type and P type transistors and a plurality of electrical connections between said first transistors and said second transistors.

7. A semiconductor device according to claim 6 wherein said second transistors are defined by a process comprising a step of etching.

8. A semiconductor device according to claim 7 wherein said step of etching comprises a lithography step and wherein said lithography step comprises:

aligning a first alignment mark associated with said first transistors using an offset calculated from;

a misalignment of said first alignment mark and a second alignment mark associated with said second transistors, and

an external parameter.

9. A semiconductor device according to claim 7 and wherein said process further comprises a step of optical annealing.

10. A semiconductor device according to claim 6 wherein substantially all vias associated with at least one of said electrical connections are less than 100 nm×

100 nm.

11. A semiconductor device according to claim 6 wherein substantially all vias associated with at least one of said electrical connections have circumscribing circles of less than 100 nm.