PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER

• US 20110199365A1
• Filed: 02/14/2011
• Published: 08/18/2011
• Est. Priority Date: 02/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Kimura, Hajime
• Granted Patent: US 8,605,073 B2
• Time in Patent Office: Days
• US Class Current: 345/212
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10⁻¹⁸ A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

Claims

1. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is electrically connected to the third wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, and a gate of the fourth transistor is electrically connected to a fifth wiring,

wherein an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

2. An electronic device comprising the display device according to claim 1 and an operation switch configured to control an image of the display device.

3. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first terminal of the third transistor is electrically connected to the second wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to third transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to third transistors is 1 aA/nm or less.

4. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is electrically connected to the second wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, and a gate of the fourth transistor is electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

5. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first terminal of the third transistor is electrically connected to the third wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to a fourth wiring,

wherein a first terminal of the fourth transistor is electrically connected to the second wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, and a gate of the fourth transistor is electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μ

m or less.

6. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is electrically connected to the third wiring, a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, and a gate of the fourth transistor is electrically connected to a fifth wiring,

wherein a first terminal of the fifth transistor is electrically connected to the second wiring, a second terminal of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fifth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fifth transistors is 1 aA/μ

m or less.

7. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, and an inverter circuit,

wherein a first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a first terminal of the second transistor is electrically connected to a third wiring, and a second terminal of the second transistor is electrically connected to the second wiring,

wherein an input terminal of the inverter circuit is electrically connected to a gate of the first transistor, and an output terminal of the inverter circuit is electrically connected to a gate of the second transistor,

wherein a channel region of each of the first transistor and the second transistor includes an oxide semiconductor, and

wherein off-state current of each of the first transistor and the second transistor is 1 aA/μ

m or less.