High Voltage Word Line Driver
First Claim
1. A word line driver circuit adapted for connection to a corresponding word line in a memory circuit, the word line driver circuit comprising:
- a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit;
a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal;
a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and
a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;
wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.
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Accused Products
Abstract
A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
60 Citations
22 Claims
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1. A word line driver circuit adapted for connection to a corresponding word line in a memory circuit, the word line driver circuit comprising:
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a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit; a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal; a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal; wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory circuit, comprising:
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at least one word line; at least one memory cell coupled to the at least one word line; and at least one word line driver circuit coupled to the at least one word line, the at least one word line driver circuit comprising; a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit; a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal; a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal; wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies.
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21. An integrated circuit, comprising:
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an embedded memory; and at least one word line driver circuit connected to a corresponding word line in the embedded memory, the at least one word line driver circuit comprising; a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a first control signal which varies as a function of an input signal supplied to the word line driver circuit; a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate adapted to receive a first clamp signal; a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate adapted to receive a second clamp signal; and a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a second voltage supply providing a second voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal; wherein the first clamp signal is set to a third voltage level configured such that a voltage difference between the first and second source/drains of the first transistor is less than a voltage difference between the first and second voltage supplies, and wherein the second clamp voltage is set to a fourth voltage level configured such that a voltage difference between the first source/drain and the second source/drain of the fourth transistor is less than the voltage difference between the first and second voltage supplies. - View Dependent Claims (22)
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Specification