Method of Dual EPI Process For Semiconductor Device

• US 20110201164A1
• Filed: 03/10/2010
• Published: 08/18/2011
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Ming-Jie, Hsieh, Bor Chiuan, Chung, Han-Pin, Wang, Shiang-Bau
• Granted Patent: US 8,609,497 B2
• Time in Patent Office: Days
• US Class Current: 438/229
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material;

forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material;

forming a protection layer over the second region to protect the second gate structure;

removing the capping layer over the first gate structure;

removing the protection layer over the second region;

epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region; and

removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

2. The method of claim 1, wherein the first material comprises silicon nitride doped with carbon.

3. The method of claim 2, wherein the third material comprises silicon nitride not doped with carbon.

4. The method of claim 1, further comprising:

prior to forming the capping layer over the first and second gate structures, forming an oxide layer over the first and second gate structures;

prior to removing the protection layer over the second region, removing the oxide layer over the first gate structure; and

after epi growing the semiconductor material, removing the oxide layer over the second gate structure by wet etching, wherein the wet etching selectively etches the oxide layer but not the first material of the spacers disposed on the sidewalls of the first gate structure.

5. The method of claim 1, wherein the epi growing the semiconductor material forms raised source and drain features at either side of the first gate structure.

6. The method of claim 1, further comprising thereafter:

forming another capping layer over the first and second gate structures, the another capping layer being formed of the second material;

forming another protection layer over the first region to protect the first gate structure;

removing the another capping layer over the second gate structure;

etching a recess in the substrate at either side of the second gate structure, the recess having sides aligned with the spacers disposed on the sidewalls of the second gate structure;

removing the another protection layer over the first region;

epitaxially growing another semiconductor material to fill the recess; and

removing the another capping layer over the first gate structure by the etching process that exhibits the etching selectivity of the second material layer to the first material

7. The method of claim 6, further comprising:

prior to forming the another capping layer over the first and second gate structures, forming an oxide layer over the first and second gate structures;

prior to removing the another protection layer over the first region, removing the oxide layer over the second gate structure; and

after epi growing the another semiconductor material, removing the oxide layer over the first gate structure by wet etching, wherein the wet etching selectively etches the oxide layer but not the first material of the spacers disposed on the sidewalls of the second gate structure.

8. The method of claim 6, wherein the semiconductor material includes silicon (Si) and wherein the another semiconductor material includes silicon germanium (SiGe)

9. The method of claim 6, wherein the first gate structure is part of an NMOS device and wherein the second gate structure is part of a PMOS device.

10. A method of fabricating a semiconductor device, comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures;

forming a first capping layer over the first and second gate structures;

forming a first protection layer over the second region to protect the second gate structure;

removing the first capping layer over the first gate structure;

removing the first protection layer over the second region;

epitaxially (epi) growing a first semiconductor material on exposed portions of the substrate in the first region;

removing the first capping layer over the second gate structure by wet etching, wherein the wet etching selectively etches the first capping layer but not the spacers disposed on the sidewalls of the first gate structure;

forming a second capping layer over the first and second gate structures;

forming a second protection layer over the first region to protect the first gate structure;

removing the second capping layer over the second gate structure;

forming a recess in the substrate at either side of the second gate structure;

removing the second protection layer over the first gate structure; and

epitaxially growing a second semiconductor material to fill the recess.

11. The method of claim 10, wherein the spacers are formed of silicon nitride doped with carbon.

12. The method of claim 11, wherein the first and second capping layers are each formed of a silicon oxide layer and a silicon nitride layer disposed over the silicon oxide layer, wherein the silicon nitride layer is not doped with carbon.

13. The method of claim 10, wherein the first semiconductor material includes silicon (Si) and wherein the second semiconductor material includes silicon germanium (SiGe).

14. The method of claim 13, wherein the first gate structure is part of an NMOS device and wherein the second gate structure is part of a PMOS device.

15. The method of claim 10, wherein the first and second protection layers are each formed of photoresist.

16. The method of claim 10, further comprising thereafter removing the second capping layer over the first gate structure by wet etching, wherein the wet etching selectively etches the second capping layer but not the spacers disposed on the sidewalls of the second gate structure.

17. A method of fabricating a semiconductor device, comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures;

forming a first capping layer over the first and second gate structures;

forming a second capping layer over the first capping layer;

forming a first protection layer over the second region to protect the second gate structure;

removing the first and second capping layers over the first gate structure;

removing the first protection layer over the second region;

epitaxially (epi) growing silicon on exposed portions of the substrate in the first region;

removing the first and second capping layers over the second gate structure by wet etching, wherein the wet etching selectively removes the first and second capping layers but not the spacers disposed on the sidewalls of the first gate structure;

forming a third capping layer over the first and second gate structures;

forming a fourth capping layer over the third capping layer;

forming a second protection layer over the first region to protect the first gate structure;

removing the third and fourth capping layers over the second gate structure;

etching a recess in the substrate at either side of the second gate structure;

removing the second protection layer over the first region;

epitaxially (epi) growing silicon germanium (SiGe) to fill the recess; and

removing the third and fourth capping layers over the first gate structure by wet etching, wherein the wet etching selectively removes the third and fourth capping layers but not the spacers disposed on the sidewalls of the second gate structure.

18. The method of claim 17, further comprising forming first and second silicon fins in third and fourth regions of the substrate, respectively, wherein the first and second silicon fins are each isolated by a shallow trench isolation (STI);

wherein the first silicon fin undergoes processing that is performed on the first gate structure such that epi Si is grown on an exposed portion of the first silicon fin; and

wherein the second silicon fin undergoes processing that is performed on the second gate structure such that the second silicon fin is etched thereby forming another recess that is surrounded by the STI, and epi SiGe is grown to fill the another recess thereby forming a SiGe fin.

19. The method of claim 17, wherein the first gate structure is part of an NMOS device and wherein the second gate structure is part of a PMOS device.

20. The method of claim 17, wherein the spacers are formed of silicon nitride doped with carbon;

wherein the first and third capping layers are formed of silicon oxide; and

wherein the second and fourth capping layers are formed of silicon nitride not doped with carbon.