IGBT AND METHOD FOR MANUFACTURING IGBT

• US 20110201187A1
• Filed: 10/15/2009
• Published: 08/18/2011
• Est. Priority Date: 10/24/2008
• Status: Abandoned Application

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Nishiwaki, Tsuyoshi, Saito, Jun
• Application Number:
  US13/124,774
• Publication Number:
  US 20110201187A1
• Time in Patent Office: Days
• US Class Current: 438/529
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A vertical IGBT includes a floating region of the first conductive type being formed within the body region of the second conductive type. A density of first conductive type impurities at a boundary of the floating region and the body region that is above the floating region is distributed to increase from an upper side to a lower side. A density of the first conductive type impurities at a boundary of the floating region and the body region that is under the floating region is distributed to decrease from an upper side to a lower side. A density of second conductive type impurities at a boundary of the floating region and the body region that is above the floating region is distributed to decrease from an upper side to a lower side. A density of the second conductive type impurities at a boundary of the floating region and the body region that is under the floating region is distributed to increase from an upper side to a lower side.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. A method for manufacturing a vertical IGBT,

the IGBT comprising:

an emitter region of a first conductive type;

a body region of a second conductive type being adjacent to the emitter region at a deeper side of the emitter region;

a drift region of the first conductive type being adjacent to the body region at a deeper side of the body region and being divided from the emitter region by the body region;

a collector region of the second conductive type being adjacent to the drift region at a deeper side of the drift region and being divided from the body region by the drift region;

a floating region of the first conductive type being formed within the body region and being divided from both of the emitter region and the drift region by the body region; and

a gate electrode facing a range of the body region and the floating region via an insulating film, the range dividing the emitter region from the drift region,

the method comprising;

(A) forming a trench at a top surface of a semiconductor substrate;

(B) forming the insulating film on an inner wall surface of the trench by a heat treatment;

(C) forming the gate electrode in the trench;

(D) injecting second conductive type impurities to the semiconductor substrate, the second conductive type impurities being injected to a depth corresponding to the body region that is above the floating region;

(E) injecting the second conductive type impurities to the semiconductor substrate, the second conductive type impurities being injected to a depth corresponding to the body region that is under the floating region; and

(F) injecting first conductive type impurities to the semiconductor substrate, the first conductive type impurities being injected to a depth corresponding to the floating region,

wherein, in (C) above, a distance in a vertical direction between a top surface of the gate electrode and the top surface of the semiconductor substrate is ensured by more than or equal to 0.2 μ

m.

9. The method of claim 5, wherein

the trench is formed at the top surface of the semiconductor substrate so that the trench extends perpendicularly to a 011 crystal orientation of the semiconductor substrate, and

the first conductive type impurities and the second conductive type impurities are injected, in a state with an angle between an injecting direction and a 100 crystal orientation of the semiconductor substrate about the 011 crystal orientation of the semiconductor substrate.

11. The method of claim 5, wherein the second conductive type impurities are injected in higher density than in (D) than in (E).

6. (canceled)

7. (canceled)

8. (canceled)

10. A method for manufacturing a vertical IGBT,

the IGBT comprising:

an emitter region of a first conductive type;

a body region of a second conductive type being adjacent to the emitter region at a deeper side of the emitter region;

a drift region of the first conductive type being adjacent to the body region at a deeper side of the body region and being divided from the emitter region by the body region;

a collector region of the second conductive type being adjacent to the drift region at a deeper side of the drift region and being divided from the body region by the drift region;

a floating region of the first conductive type being formed within the body region and being divided from both of the emitter region and the drift region by the body region; and

a gate electrode facing a range of the body region and the floating region via an insulating film, the range dividing the emitter region from the drift region,

the method comprising;

(A) forming a trench at a top surface of a semiconductor substrate;

(B) forming the insulating film on an inner wall surface of the trench by a heat treatment;

(C) forming the gate electrode in the trench;

(D) injecting second conductive type impurities to the semiconductor substrate, the second conductive type impurities being injected to a depth corresponding to the body region that is above the floating region;

(E) injecting the second conductive type impurities to the semiconductor substrate, the second conductive type impurities being injected to a depth corresponding to the body region that is under the floating region; and

(F) injecting first conductive type impurities to the semiconductor substrate, the first conductive impurities being injected to a depth corresponding to the floating region;

wherein

the trench is formed at the top surface of the semiconductor substrate so that the trench extends perpendicularly to a 011 crystal orientation of the semiconductor substrate, and

the first conductive type impurities and the second conductive type impurities are injected, in a state with an angle between an impurities injecting direction and a 100 crystal orientation of the semiconductor substrate about the 011 crystal orientation of the semiconductor substrate.