Method and Apparatus for Versatile Controllability and Observability in Prototype System

• US 20110202894A1
• Filed: 02/11/2011
• Published: 08/18/2011
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: SpringSoft, Inc. (Synopsys Incorporated), Springsoft USA Incorporated (Synopsys Incorporated)
• Inventors: Shei, Swey-Yan, Hsu, Yu-Chin, Chang, Ying-Tsai, Mao, Hwa, Wang, Ming-Yang
• Granted Patent: US 8,281,280 B2
• Time in Patent Office: Days
• US Class Current: 716/108
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.

Claims

1. A test system comprising:

a first interface component configured to provide a configured image representative of at least a portion of a user design and an associated verification module;

a second interface component configured to provide timing and control information to the associated verification module based on at least one of the configured image and runtime control information received from the first interface component;

the associated verification module coupled with the second interface component, the associated verification module being configured to control the device and monitor the device state of the at least a portion of the user design in response to the timing and control information from the second interface component.

2. The test system of claim 1, wherein the configured image comprises at least one of a field programmable gate array (FPGA) image and control and timing information.

3. The test system of claim 1, wherein the first interface component is further configured to send commands for reconfiguring the configured image.

4. The test system of claim 1, wherein control information received from the first interface includes information that leads the verification module to create a trigger condition.

5. The test system of claim 3, wherein the trigger condition is based at least in part on timing information received from the second interface component.

6. The test system of claim 1, wherein control information received from the first interface includes information that leads the verification module to probe a signal.

7. The test system of claim 1, wherein the second interface component is physically co-located with the device.

8. The test system of claim 1, wherein the second interface component comprises a controller configured to encode and decode data exchanged with the verification module.

9. The test system of claim 8, wherein the controller is further configured to provide clock and reset signals to the verification module.

10. The test system of claim 1, wherein the verification module comprises:

a first circuit configured to connect to and probe predetermined signals located within the device; and

a second circuit configured to perform at least one of decoding and encoding data exchanged with the second interface component.

11. The test system of claim 10, wherein the predetermined signals may be based in part on register transfer language (RTL) information included in a design database coupled to the first interface component.

12. The test system of claim 1, wherein the verification module is configured to perform at least one of co-simulation and co-emulation verification tests in response to receiving clock and reset signals from the second interface component.

13. A method comprising:

receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module;

sending, using the first interface component, the configured image to a device;

sending, using a second interface component, timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component; and

controlling, using the verification module, the device in response to the timing and control information from the second interface component.

14. The method of claim, 13 further comprising:

creating, using the second interface component, a trigger condition based on control information received from the first interface component, wherein the trigger condition leads the verification module to capture data associated with a predetermined signal associated with a portion of the user design.

15. The method of claim 14, wherein the trigger condition is based in part on timing information received from the second interface component.

16. The method of claim 13, wherein control information received from the first interface includes information leading the verification module to probe a predetermined signal.

17. The method of claim 13, wherein controlling, using the verification module, the device in response to the timing and control information from the second interface component comprises sampling a predetermined signal based on timing information received from the second interface component.

18. The method of claim 17, wherein sampling is performed synchronously.

19. The method of claim 13, wherein controlling, using the verification module, the device in response to the timing and control information from the second interface component comprises sampling a first predetermined signal based on second predetermined signal in an asynchronous manner.

20. The method of claim 13, wherein the verification module is configured to perform at least one of co-simulation and co-emulation verification tests in response to at least one of timing and control signal from the second interface component.

21. A method comprising:

receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module;

sending, using the first interface component, the configured image to a device;

sending, using a second interface component, timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component; and

monitoring, using the verification module, the device state of at least a portion of the user design in response to the receiving timing and control information from the second interface component; and

capturing, using the verification module, information representative of at least a portion of the user design.

22. The method of claim 21, wherein the first interface component is further configured to send commands for reconfiguring the configured image.

23. The method of claim 22, wherein reconfiguring the configured image comprises:

receiving a modified FPGA image; and

reconfiguring data-dependent circuitry of the modified FPGA image associated with the verification module.

24. The method of claim 22, wherein the timing information is provided a source external to the second interface component.

25. The method of claim 22, wherein the configured image is configured to perform at least one of co-simulation and co-emulation verification tests in response to receiving at least one of timing and control signal from the second interface component.

26. A computer readable storage medium comprising instructions that when executed by a processor, cause the processor to perform the method comprising:

receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module;

sending, using the first interface component, the configured image to a device;

sending, using a second interface component, timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component; and

monitoring, using the verification module, the device state of at least a portion of the user design in response to the receiving timing and control information from the second interface component; and

capturing, using the verification module, information representative of at least a portion of the user design.