METHOD FOR INTEGRATING AN ELECTRONIC COMPONENT INTO A PRINTED CIRCUIT BOARD

• US 20110203107A1
• Filed: 10/28/2009
• Published: 08/25/2011
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Merl, Klaus, Lenhardt, Patrick, Schrittwieser, Wolfgang
• Granted Patent: US 8,914,974 B2
• Time in Patent Office: Days
• US Class Current: 29/841
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/2402 Laminated, e.g. MCM-L type
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/83132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/188 : manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09918 : Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 2203/0554 : Metal used as mask for etching vias, e.g. by laser ablation
• CPC Class Codes: H05K 2203/108 : Using a plurality of lasers or laser light with a plurality of wavelengths
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components
• CPC Class Codes: H05K 3/0035 : of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0038 : combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/025 : by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

The invention relates to a method for integrating an electronic component into a printed circuit board, whereby the electronic component (4) comprising contacts (6) oriented towards the insulating layer (1) is fixed to a laminate at least consisting of a conducting or conductive layer (2) and a non-conducting or insulating layer (1). According to the invention, once the component (4) has been fixed to the insulating layer (1), holes or perforations (8, 11) corresponding to the contacts (6) of the component (4) are formed in the conducting layer (2) and in the insulating layer (1), the contacts coming into contact with the conducting layer (2), enabling a reliable integration or embedding of an electronic component (4) into a printed circuit board.

Claims

1. A method for integrating an electronic component into a printed circuit board, whereby the electronic component comprising contacts oriented towards the insulating layer is fixed to a laminate at least consisting of a conducting or conductive layer and a non-conducting or insulating layer, wherein, once the component has been fixed to the insulating layer, holes or perforations corresponding to the contacts of the component are formed in the conducting layer and in the insulating layer, and the contacts are subsequently contacted with the conducting layer.

2. A The method according to claim 1, wherein the electronic component, once it has been fixed to the insulating layer, is surrounded or sheathed by an insulating material, particularly at least one prepreg sheet and/or a resin, in a manner known per se.

3. A The method according to claim 2, wherein the sheathing of the electronic component is realized by a pressing or laminating procedure of a plurality of insulating layers.

4. A The method according to claim 1, wherein the electronic component is fixed to the insulating layer in a manner known per se using an adhesive.

5. The method according to claim 4, wherein a thermally conducting or conductive adhesive material, e.g. an adhesive or an adhesive tape, is used.

6. The method according to claim 1, wherein the holes or perforations in the conducting layer are formed by a drilling procedure, particularly laser drilling, or an etching procedure.

7. The method according to claim 1, wherein that the formations of the holes or perforations in the conducting layer and in the insulating layer are performed in separate method steps after the fixation of the component.

8. The method according to claim 7, wherein an UV laser is used when forming the holes or perforations in the conducting layer separately.

9. The method according to claim 1, wherein the holes or perforations in the insulating layer are made by a laser, particularly a CO₂ laser.

10. The method according to claim 9, wherein a laser beam whose dimension or diameter exceeds the clear width of the holes or perforations in the conducting layer is used for separately forming the holes or perforations in the insulating layer.

11. The method according to claim 9, wherein for separately forming the holes or perforations in the insulating layer a laser, particularly a pulsed CO₂ laser, having a power of 0.1 to 75 W, particularly 0.1 to 7 W, is used for a period or pulse length of 0.1 to 20 μ

s.

12. The method according to claim 1, wherein the holes or perforations in the conducting layer and in the insulating layer are formed in a common method step using a CO₂ laser after a pretreatment of the conducting layer.

13. The method according to claim 12, wherein said pretreatment of the conducting layer comprises the formation of a copper oxide layer on the conducting layer, which is, in particular, covered by an additional organic or metallo-organic layer.

14. The method according to claim 12, wherein a pulse duration of the CO₂ laser of at least 200 μ

s, particularly at least 250 μ

s, and a maximum pulse count of 5, particularly 3, are chosen to remove the conducting layer and the insulating layer in a common method step.

15. The method according to claim 12, wherein that the additional layer applied as a pretreatment of the conducting layer is removed, particularly by an etching step, after the formation of the holes or perforations and prior to further processing steps.

16. The method according to claim 1, wherein, prior to fixing the component to the insulating layer, at least one marker is formed at least in the insulating layer for registering and aligning the component on the insulating layer.

17. The method according to claim 16, wherein the at least one marker is formed by a bore or perforation penetrating both the insulating layer and the conducting layer.

18. The method according to claim 1, wherein, in addition to forming holes or perforations corresponding to the contacts of the component in the conducting layer and in the non-conducting layer, at least one further perforation is formed outside the region of the fixation of the component to the laminate for providing an additional perforation for the formation of a subsequent feedthrough and/or for the formation of the contour of a circuit board element.

19. The method according to claim 18, wherein the additional perforation is formed relative to the previously produced marker.

20. The method according to claim 18, wherein the laser beam(s) provided for forming the perforations or holes in the conducting and insulating layers is/are used for forming the perforation for the feedthrough and/or contour.

21. The method according to claim 1, wherein, prior to fixing the component, at least one carrier or protection layer is provided on the conducting layer, on its surface facing away from the insulating layer, which is removed again prior to forming the holes or perforations in the conducting layer, particularly after sheathing of the component.

22. The method according to claim 21, wherein a carrier or protection layer is formed by a metallic sheet or polymer.

23. The method according to claim 1, wherein the insulating layer facing the component is formed by a layer improving the adherence between the conducting layer and the material surrounding the component, e.g. a metallo-organic layer or a resin layer or the like.

24. The method according to claim 1, wherein the conducting layer for contacting the contacts of the component and/or the conducting layer of the laminate for forming a conducting pattern is applied and/or patterned by a semi-additive or subtractive method.