TEST POINT DESIGN FOR A HIGH SPEED BUS
First Claim
1. A test point design comprising;
- a. a circuit board comprising a plurality of layers including a power plane and a ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and
a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to the second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed.
1 Assignment
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Accused Products
Abstract
A circuit board includes a pair of differential signal lines and a pair of test point pads, one test point pad coupled to one of the signal lines and another of the test point pads coupled to another of the signal lines. The two test point pads are staggered relative to each other and the two signal lines. The circuit board includes a plurality of conductive layers and a plurality of insulating layers. The conductive layers can be etched into conductive patterns, or traces, for connecting the electronic components, which are soldered to the circuit board. The conductive layers may be selectively connected together by vias. One or more of the conductive layers may be a metal plane for providing a ground plane and/or a power plane. To minimize or eliminate the capacitance generated between the test point pad and an underlying ground plane and/or power plane, portions of the ground plane and/or the portion of the power plane directly aligned with each test point pad are removed.
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Citations
26 Claims
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1. A test point design comprising;
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a. a circuit board comprising a plurality of layers including a power plane and a ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to the second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of configuring a test point design for a circuit board including a power plane and a ground plane, the method comprising;
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a. removing a first portion of the power plane from a first position on the power plane that is to be aligned with a first test point pad on an outer layer of the circuit board; b. removing a second portion of the power plane from a second position on the power plane that is to be aligned with a second test point pad on the outer layer of the circuit board; c. removing a first portion of the ground plane from a first position on the ground plane that is to be aligned with the first test point pad, wherein the first position on the ground plane is aligned with the first position on the power plane; d. removing a second portion of the ground plane from a second position on the ground plane that is to be aligned with the second test point pad, wherein the second position on the ground plane is aligned with the second position on the power plane; e. adding a pair of differential signal lines to the outer layer of the circuit board, wherein the pair of differential signal lines includes a first signal line and a second signal line; and f. adding the first test point pad and the second test point pad to the outer layer of the circuit board, wherein the first test point pad is connected to the first signal line and the second test point pad is connected to the second signal line. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification