Arrangement Comprising at Least One Power Semiconductor Module and a Transport Packaging

• US 20110203967A1
• Filed: 01/20/2011
• Published: 08/25/2011
• Est. Priority Date: 01/20/2010
• Status: Active Grant

• Current Assignee: Semikron Elektronik GmbH & Company KG (Heilbronner Holding GbR)
• Original Assignee: Semikron Elektronik GmbH & Company KG (Heilbronner Holding GbR)
• Inventors: STAROVECKÝ, Stefan
• Granted Patent: US 8,405,195 B2
• Time in Patent Office: Days
• US Class Current: 206/710
• CPC Class Codes: B65D 2575/3245 by peeling off the non-rigid sheet
• CPC Class Codes: B65D 75/327 and forming several compartments
• CPC Class Codes: B65D 75/367 and forming several compartments

Abstract

An arrangement comprising: at least one power semiconductor module and a transport packaging. The power semiconductor module has a base element, a housing and connection elements. The transport packaging has a cover layer, an interlayer with a respective cutout assigned to the power semiconductor module, and a cover film. The cover layer is generally planar, and has a first main surface facing the power semiconductor module. The interlayer is arranged on the first main surface of the cover layer. The power semiconductor module is arranged in the cutout, on the first main surface of the cover layer, wherein the base element of the power semiconductor module is disposed on the first main surface of the cover layer. The cover film bears on and covers substantial parts of the housing of the power semiconductor module. The cover film is connected to the first main surface of the interlayer.

Claims

1. An arrangement comprising:

at least one power semiconductor module having a base element, a housing and connection elements; and

a transport packaging having

a generally planar cover layer, said cover layer including a first main surface facing said at least one power semiconductor module;

an interlayer with a respective cutout assigned to each of said at least one power semiconductor modules, and including a second main surface disposed on said first main surface of said cover layer; and

a cover film;

wherein said at least one power semiconductor module is arranged in said at least one cutout on said first main surface of said cover layer and, consequently, becomes situated on said first main surface of the cover layer, wherein said cover film covers substantial parts of said at least one power semiconductor module, and therefore bears substantially against said housing, and

wherein said cover film is connected to said first main surface of said interlayer.

2. The arrangement of claim 1, wherein said cover layer and said interlayer are detachably connected.

3. The arrangement of claim 1, wherein said cover film is detachably connected to said first main surface of said cover layer in an intermediate region cut free by a respective one of said at least one cutout alongside a respective one of said at least one power semiconductor component.

4. The arrangement of claim 1,

wherein said at least one power semiconductor module is a plurality of power semiconductor modules arranged in a matrix;

and

wherein adjacent ones of said plurality of power semiconductor modules are separated from one another, in at least one direction parallel to said first main surface of said cover layer and parallel to a normal to the surface of said housing, by a distance that is greater than a width of said housing in said direction.

5. The arrangement of claim 1,

wherein said at least one power semiconductor module is a plurality of power semiconductor modules arranged in a matrix;

and

wherein said transport packaging includes a perforation between adjacent ones of said power semiconductor components.

6. The arrangement of claim 1, wherein said cover film is a plastic film.

7. The arrangement of claim 6, wherein said cover film is a conductive plastic film

8. The arrangement of claim 6, wherein said cover film is a dissipative plastic film

9. The arrangement of claim 6, wherein said cover film has a metal-vapor-deposited outer surface.

10. The arrangement of claim 1, wherein said cover film is at least partly transparent at least in sections.

11. The arrangement of claim 10, wherein said cover film is substantially completely transparent.

12. The arrangement of claim 1, wherein at least one of said interlayer and said cover layer is formed of a material selected from the group consisting of paperboard, cardboard and composite cardboard.

13. The arrangement of claim 1, wherein at least one of said interlayer and said cover layer is conductive.

14. The arrangement of claim 1, wherein at least one of said interlayer and said cover layer is dissipative.

15. The arrangement of claim 2, wherein the detachable connection between said cover layer and said interlayer has a lower adhesive force than the connection between said interlayer and said cover film.

16. The arrangement of claim 1, wherein an edge of said cutout bears to the extent of no more than about 50% directly against the respective power semiconductor module and the remaining part of said edge is at a distance of at least 2 mm from said respective power semiconductor module.

17. The arrangement of claim 16, wherein said edge of said cutout bears to the extent of no more than about 25% directly against the respective power semiconductor module.

18. The arrangement of claim 1, wherein said cover layer is thinner than said interlayer.

19. The arrangement of claim 18, wherein said cover layer has a thickness of between about 0.2 mm and about 1 mm and said interlayer has a thickness of between about 0.5 and about 3 mm.