Thin-Film Transistor Substrate, Method of Manufacturing the Same, and Display Device Including the Same

• US 20110204370A1
• Filed: 02/15/2011
• Published: 08/25/2011
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Hyun-Jung, Kim, Ki-Won, Kim, Bong-Kyun, Lee, Woo-Geun, Yang, Sung-Hoon, Yoon, Kap-Soo
• Granted Patent: US 8,445,301 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 50/805 Electrodes
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

Provided are a thin-film transistor (TFT) substrate, a method of manufacturing the same, and a display device including the same. The TFT substrate includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, an oxide semiconductor pattern formed on the gate insulating layer, a source electrode formed on the oxide semiconductor pattern, a drain electrode formed on the oxide semiconductor pattern to face the source electrode, and a pixel electrode formed on the gate insulating layer.

Claims

1. A thin-film transistor (TFT) substrate comprising:

a gate electrode formed on a substrate,

a gate insulating layer formed on the gate electrode;

an oxide semiconductor pattern formed on the gate insulating layer;

a source electrode formed on the oxide semiconductor pattern;

a drain electrode formed on the oxide semiconductor pattern, the drain electrode facing the source electrode, and

a pixel electrode formed on the gate insulating layer.

2. The TFT substrate of claim 1, wherein the pixel electrode extends from the oxide semiconductor pattern.

3. The TFT substrate of claim 1, further comprising a passivation film formed on the source electrode and the drain electrode, the passivation film exposing the pixel electrode.

4. The TFT substrate of claim 1, wherein the pixel electrode and the oxide semiconductor pattern are made of a same material and the pixel electrode is plasma-treated.

5. The TFT substrate of claim 4, wherein the pixel electrode is plasma-treated with a hydrogen-containing gas.

6. The TFT substrate of claim 1, further comprising one or more oxide semiconductor protection film patterns formed between the source and drain electrodes and the oxide semiconductor pattern.

7. The TFT substrate of claim 1, wherein a side of the oxide semiconductor pattern and the source electrode share an etched surface.

8. The TFT substrate of claim 6, wherein the one or more oxide semiconductor protection film patterns each have a contact region which is plasma-treated with a hydrogen-containing gas.

9. The TFT substrate of claim 8, wherein the contact regions of the one or more oxide semiconductor protection film patterns electrically connect the pixel electrode and the drain electrode.

27. The TFT substrate of claim 1, wherein the pixel electrode is spaced apart from the oxide semiconductor pattern.

28. The TFT substrate of claim 27, wherein the pixel electrode contacts the drain electrode and wherein an upper surface of the pixel electrode contacts a lower surface of the drain electrode.

10. A method of manufacturing a TFT substrate, the method comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode;

forming an oxide semiconductor pattern on the gate insulating layer; and

forming a source electrode and a drain electrode on the oxide semiconductor pattern, wherein the drain electrode faces the source electrode.

11. The method of claim 10, wherein the pixel electrode is formed extending from the oxide semiconductor pattern.

12. The method of claim 10, wherein the forming of the oxide semiconductor pattern and the forming of the source and drain electrodes comprise:

forming an oxide semiconductor layer on the gate insulating layer;

forming a conductive layer on the oxide semiconductor layer;

forming a first photosensitive film pattern on the conductive layer; and

forming the oxide semiconductor pattern and a pixel electrode pattern by etching the oxide semiconductor layer using the first photosensitive film pattern and forming a conductive layer pattern by etching the conductive layer,

wherein the first photosensitive film pattern comprises a first region and a second region which is thinner than the first region.

13. The method of claim 12, wherein the source electrode and the drain electrode are formed by etching the conductive layer pattern, wherein the conductive layer pattern is formed by using a second photosensitive film pattern having the second region removed.

14. The method of claim 12, wherein the first photosensitive film pattern is formed using a halftone mask or a slit mask.

15. The method of claim 12, wherein a side of the oxide semiconductor pattern shares an etched surface with the source electrode.

16. The method of claim 12, wherein the pixel electrode pattern extends from the oxide semiconductor pattern.

17. The method of claim 16, further comprising, before the forming of the pixel electrode, forming a passivation film covering the source electrode and the drain electrode and exposing the pixel electrode pattern.

18. The method of claim 17, wherein the forming of the pixel electrode comprises performing a plasma-treatment process on the pixel electrode pattern.

19. The method of claim 18, wherein the plasma-treatment process is performed using a hydrogen-containing gas.

20. The method of claim 18, wherein the plasma-treatment process is performed using a high-frequency RF power of approximately 100 to 400 mW/cm²-time.

21. The method of claim 10, further comprising forming one or more oxide semiconductor protection film patterns between the oxide semiconductor pattern and the source and drain electrodes.

22. The method of claim 21, further comprising forming a contact region by performing a plasma-treatment process on the one or more oxide semiconductor protection film patterns using a hydrogen-containing gas.

23. The method of claim 22, wherein the contact region of the one or more oxide semiconductor protection film patterns electrically connects the pixel electrode and the drain electrode.

24. A display device comprising:

a TFT substrate comprising a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, an oxide semiconductor pattern formed on the gate insulating layer, a source electrode formed on the oxide semiconductor pattern, a drain electrode formed on the oxide semiconductor pattern, the drain electrode is spaced apart from the source electrode, and a pixel electrode formed on the gate insulating layer and extending from the oxide semiconductor pattern; and

a common electrode facing the pixel electrode.

25. The display device of claim 24, further comprising an organic light-emitting layer formed between the common electrode and the pixel electrode.

26. The display device of claim 24, further comprising:

an opposite substrate comprising the common electrode, the opposite substrate facing the TFT substrate; and

a liquid crystal layer interposed between the TFT substrate and the opposite substrate.