Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame

• US 20110204472A1
• Filed: 04/30/2011
• Published: 08/25/2011
• Est. Priority Date: 05/18/2009
• Status: Abandoned Application

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Lin, Yaojian
• Application Number:
  US13/098,419
• Publication Number:
  US 20110204472A1
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors.

Claims

1. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

forming an inductor core over the carrier;

mounting a pillar frame over the carrier and semiconductor component, the pillar frame including a plurality of bodies with a first portion of the bodies being disposed around the inductor core;

depositing an encapsulant around the semiconductor component, plurality of bodies, and inductor core;

removing a portion of the pillar frame while leaving the first portion of the bodies to form inductor pillars;

forming a first interconnect structure over a first surface of the encapsulant;

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

2. The method of claim 1, wherein the inductor core includes ferromagnetic material.

3. The method of claim 1, wherein removing the portion of the pillar frame further leaves a second portion of the bodies to form an interconnect pillar.

4. The method of claim 3, further including stacking a plurality of the semiconductor components electrically connected through the interconnect pillar.

5. The method of claim 3, further including disposing a plurality of the semiconductor components side-by-side electrically connected through the interconnect pillar.

6. The method of claim 1, further including forming a shielding layer over the semiconductor component.

7. The method of claim 1, further including forming an integrated passive device within the first or second interconnect structures.

8. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

mounting a pillar frame over the carrier and semiconductor component;

depositing an encapsulant over the semiconductor component and pillar frame;

removing a portion of the pillar frame, wherein a first remaining portion of the pillar frame provides inductor pillars;

forming a first interconnect structure over a first surface of the encapsulant;

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

9. The method of claim 8, wherein a second remaining portion of the pillar frame provides an interconnect pillar.

10. The method of claim 8, wherein the first or second interconnect structure is electrically connected to a contact pad of the semiconductor component.

11. The method of claim 8, further including forming a shielding layer over the semiconductor component.

12. The method of claim 8, further including forming an integrated passive device within the first or second interconnect structures.

13. The method of claim 8, further including forming a discrete semiconductor component over the first interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

mounting a pillar frame over the carrier and semiconductor component;

depositing an encapsulant over the semiconductor component and pillar frame;

removing a portion of the pillar frame, wherein a first remaining portion of the pillar frame provides inductor pillars; and

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the inductor pillars to form a 3D inductor.

15. The method of claim 14, further including:

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form the 3D inductor.

16. The method of claim 15, further including forming an integrated passive device within the first or second interconnect structures.

17. The method of claim 14, further including forming an inductor core over the carrier, the inductor pillars being disposed around the inductor core.

18. The method of claim 14, wherein a second remaining portion of the pillar frame provides an interconnect pillar.

19. The method of claim 14, further including forming a shielding layer over the semiconductor component.

20. The method of claim 14, further including forming a plurality of 3D inductors with the inductor pillars.

21. A semiconductor device, comprising:

a semiconductor component;

an inductor core disposed in proximity to the semiconductor component;

a pillar frame mounted over the semiconductor component and inductor core;

an encapsulant deposited over the semiconductor component, pillar frame, and inductor core, wherein a portion of the pillar frame is removed to form inductor pillars around the inductor core;

a first interconnect structure formed over a first surface of the encapsulant; and

a second interconnect structure formed over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

22. The semiconductor device of claim 21, wherein removing the portion of the pillar frame leaves an interconnect pillar.

23. The semiconductor device of claim 21, further including a shielding layer formed over the semiconductor component.

24. The semiconductor device of claim 21, further including an integrated passive device formed within the first or second interconnect structures.

25. The semiconductor device of claim 21, further including a plurality of 3D inductors formed with the inductor pillars.