CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME

• US 20110204510A1
• Filed: 04/29/2011
• Published: 08/25/2011
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chiu-Ming, Lin, Mou-Shiung, Chou, Chien-Kang, Lo, Hsin-Jung
• Granted Patent: US 8,159,074 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05673 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05676 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.

Claims

1-20. -20. (canceled)

21. A semiconductor chip comprising:

a semiconductor substrate;

a transistor in or on said semiconductor substrate;

a first metal interconnect over said semiconductor substrate, wherein said first metal interconnect comprises electroplated copper;

a second metal interconnect over said semiconductor substrate, wherein said second metal interconnect has a portion spaced apart from said first metal interconnect;

a third metal interconnect over said semiconductor substrate, wherein said third metal interconnect has a portion spaced apart from said first metal interconnect and from said second metal interconnect;

an insulating layer over said semiconductor substrate, wherein a first opening in said insulating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, wherein a second opening in said insulating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, and wherein a third opening in said insulating layer is over a third contact point of said third metal interconnect, and said third contact point is at a bottom of said third opening, wherein said insulating layer comprises a nitride layer;

a fourth metal interconnect on said first and second contact points and over said insulating layer, wherein said first contact point is connected to said second contact point through said fourth metal interconnect, wherein said fourth metal interconnect comprises a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer;

a metal bump connected to said third contact point through said third opening, wherein said metal bump comprises a tin-containing layer having a thickness between 10 and 300 micrometers; and

a dielectric layer on a top surface of said fourth metal interconnect and over a top surface of said insulating layer, wherein there is no opening in said dielectric layer on said top surface of said fourth metal interconnect, wherein said metal bump has a top higher than a top surface of said dielectric layer.

22. The semiconductor chip of claim 21, wherein said first metal layer comprises titanium.

23. The semiconductor chip of claim 21, wherein said first metal layer comprises titanium nitride.

24. The semiconductor chip of claim 21, wherein said first metal layer comprises tantalum.

25. The semiconductor chip of claim 21, wherein said first metal layer comprises tantalum nitride.

26. The semiconductor chip of claim 21, wherein said metal bump further comprises a titanium-containing layer under said tin-containing layer.

27. The semiconductor chip of claim 21, wherein said metal bump comprises a copper-containing layer under said tin-containing layer.

28. The semiconductor chip of claim 21, wherein said metal bump comprises a nickel-containing layer under said tin-containing layer.

29. The semiconductor chip of claim 21, wherein there is no polymer layer between said fourth metal interconnect and said insulating layer.

30. The semiconductor chip of claim 21 further comprising a polymer layer on said insulating layer, wherein said fourth metal interconnect is further on said polymer layer.

31. The semiconductor chip of claim 21, wherein said dielectric layer comprises a polymer.

32. The semiconductor chip of claim 21, wherein said nitride layer has a thickness between 0.2 and 1.2 micrometers.

33. The semiconductor chip of claim 21, wherein said second metal layer comprises copper.

34. A circuit component comprising:

a semiconductor chip comprising a semiconductor substrate, a transistor in or on said semiconductor substrate, a first metal interconnect over said semiconductor substrate, a second metal interconnect over said semiconductor substrate, wherein said second metal interconnect has a portion spaced apart from said first metal interconnect, a third metal interconnect over said semiconductor substrate, wherein said third metal interconnect has a portion spaced apart from said first metal interconnect and from said second metal interconnect, a passivation layer over said semiconductor substrate, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, and wherein a third opening in said passivation layer is over a third contact point of said third metal interconnect, and said third contact point is at a bottom of said third opening, a fourth metal interconnect on said first and second contact points and over said passivation layer, wherein said first contact point is connected to said second contact point through said fourth metal interconnect, a metal bump connected to said third contact point through said third opening, and a dielectric layer over a top surface of said fourth metal interconnect and a top surface of said passivation layer, wherein there is no opening in said dielectric layer over said top surface of said fourth metal interconnect; and

a device comprising a glass substrate and a pad connected to said metal bump.

35. The circuit component of claim 34, wherein said first metal interconnect comprises aluminum.

36. The circuit component of claim 34, wherein said first metal interconnect comprises electroplated copper.

37. The circuit component of claim 34, wherein said passivation layer comprises a nitride layer.

38. The circuit component of claim 34, wherein there is no polymer layer between said fourth metal interconnect and said passivation layer.

39. The circuit component of claim 34 further comprising a polymer layer on said passivation layer, wherein said fourth metal interconnect is further on said polymer layer.

40. The circuit component of claim 34, wherein said fourth metal interconnect comprises an adhesion layer and a copper layer over said adhesion layer, wherein said copper layer has a thickness between 2 and 30 micrometers.

41. The circuit component of claim 34, wherein said metal bump comprises an adhesion layer and a tin-containing layer over said adhesion layer.