DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND DRIVING METHOD THEREOF

• US 20110204928A1
• Filed: 02/11/2011
• Published: 08/25/2011
• Est. Priority Date: 02/23/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Kimura, Hajime
• Granted Patent: US 8,599,998 B2
• Time in Patent Office: Days
• US Class Current: 327/109
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line, and

wherein each channel region of the second transistor and the third transistor is formed using an oxide semiconductor.

2. The semiconductor device according to claim 1,

wherein each off-state current of at least the second transistor and the third transistor is 1 aA/μ

m or less.

3. The semiconductor device according to claim 1,

wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

4. The semiconductor device according to claim 1,

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor.

5. A display device comprising the semiconductor device according to claim 1.

6. The semiconductor device according to claim 1 further comprising:

a fourth transistor;

a fifth transistor; and

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line.

7. The semiconductor device according to claim 6 further comprising:

a sixth transistor; and

a capacitor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor, and

wherein a first electrode of the capacitor is electrically connected to the first line, and a second electrode of the capacitor is electrically connected to the gate of the fourth transistor.

8. A semiconductor device comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line, and

wherein each channel region of the first to third transistors is formed using an oxide semiconductor.

9. The semiconductor device according to claim 8,

wherein each off-state current of the first to third transistors is 1 aA/μ

m or less

10. The semiconductor device according to claim 8,

wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

11. The semiconductor device according to claim 8,

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor.

12. A display device comprising the semiconductor device according to claim 8.

13. The semiconductor device according to claim 8 further comprising:

a fourth transistor; and

a fifth transistor;

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line.

14. The semiconductor device according to claim 13 further comprising:

a sixth transistor; and

a capacitor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor, and

wherein a first electrode of the capacitor is electrically connected to the first line, and a second electrode of the capacitor is electrically connected to the gate of the fourth transistor.

15. A driving method of a semiconductor device comprising a first transistor, a second transistor, and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line, and

wherein each channel region of the second transistor and the third transistor is formed using an oxide semiconductor,

the driving method comprising the steps of:

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a first period;

turning on the third transistor, thereby establishing electrical continuity between the third line and a gate of the first transistor in the first period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a second period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a third period;

turning on the second transistor, thereby establishing electrical continuity between the second line and the gate of the first transistor in the third period; and

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a fourth period.

16. The driving method of a semiconductor device according to claim 15,

wherein each off-state current of at least the second transistor and the third transistor is 1 aA/μ

m or less.

17. The driving method of a semiconductor device according to claim 15,

wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

18. The driving method of a semiconductor device according to claim 15,

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor.

19. The driving method of a semiconductor device according to claim 15, the semiconductor device further comprising:

a fourth transistor;

a fifth transistor; and

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line,

the driving method further comprising the steps of;

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the first to third periods,

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the first to third periods,

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the fourth period, and

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the fourth period.

20. The driving method of a semiconductor device according to claim 19, the semiconductor device further comprising a sixth transistor wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,

the driving method further comprising the step of:

turning on the sixth transistor, thereby establishing electrical continuity between the fourth line and the gate of the fourth transistor in the first to fourth periods.

21. A driving method of a semiconductor device comprising a first transistor, a second transistor, and a third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first line, and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line, the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and a gate of the second transistor is electrically connected to the first line,

wherein one of a source and a drain of the third transistor is electrically connected to a third line, the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and a gate of the third transistor is electrically connected to the third line, and

wherein each channel region of the second transistor and the third transistor is formed using an oxide semiconductor,

the driving method comprising the steps of:

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a first period;

turning on the third transistor, thereby establishing electrical continuity between the third line and a gate of the first transistor in the first period;

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the first period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a second period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the second period;

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the second period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a third period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the third period;

turning on the second transistor, thereby establishing electrical continuity between the second line and the gate of the first transistor in the third period;

turning on the first transistor, thereby establishing electrical continuity between the first line and the second line in a fourth period;

turning off the third transistor, thereby breaking electrical continuity between the third line and the gate of the first transistor in the fourth period; and

turning off the second transistor, thereby breaking electrical continuity between the second line and the gate of the first transistor in the fourth period.

22. The driving method of a semiconductor device according to claim 21,

wherein each off-state current of at least the second transistor and the third transistor is 1 aA/μ

m or less.

23. The driving method of a semiconductor device according to claim 21,

wherein a ratio of a channel width to a channel length of the first transistor is twice or more and less than 20 times a ratio of a channel width to a channel length of the third transistor.

24. The driving method of a semiconductor device according to claim 21,

wherein a ratio of a channel width to a channel length of the second transistor is 0.1 times or more and less than 1 time a ratio of a channel width to a channel length of the third transistor.

25. The driving method of a semiconductor device according to claim 21, the semiconductor device further comprising:

a fourth transistor;

a fifth transistor; and

wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth line, the other of the source and the drain of the fourth transistor is electrically connected to the second line, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth line, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a fifth line,

the driving method further comprising the steps of;

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the first to third periods,

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the first to third periods,

turning off the fourth transistor, thereby breaking electrical continuity between the fourth line and the second line in the fourth period, and

turning off the fifth transistor, thereby breaking electrical continuity between the fourth line and the gate of the first transistor in the fourth period.

26. The driving method of a semiconductor device according to claim 25, the semiconductor device further comprising a sixth transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth line, the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,

the driving method further comprising the step of:

turning on the sixth transistor, thereby establishing electrical continuity between the fourth line and the gate of the fourth transistor in the first to fourth periods.