INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20110205720A1
• Filed: 02/18/2011
• Published: 08/25/2011
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Granted Patent: US 8,471,361 B2
• Time in Patent Office: Days
• US Class Current: 361/782
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10T 29/5313 : Means to assemble electrical device
• CPC Class Codes: Y10T 29/5317 : Laminated device

Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Claims

1-20. -20. (canceled)

21. A circuit component comprising:

an organic substrate;

a die over said organic substrate, wherein said die comprises multiple active devices;

a glass substrate over said die and said organic substrate, where a first opening in said glass substrate passes vertically through said glass substrate; and

a first interconnecting structure comprising a first portion in said first opening and a second portion over said glass substrate, wherein said second portion is connected to said die through said first portion.

22. The circuit component of claim 21, wherein said organic substrate comprises a printed circuit board.

23. The circuit component of claim 21 further comprising a polymer layer between said organic substrate and said glass substrate and in contact with a sidewall of said die.

24. The circuit component of claim 21, wherein said glass substrate has a thickness between 2 and 200 micrometers.

25. The circuit component of claim 21, wherein said glass substrate has a width greater than that of said die.

26. The circuit component of claim 21, wherein said first interconnecting structure comprises copper.

27. The circuit component of claim 21, wherein said first interconnecting structure comprises electroplated copper.

28. The circuit component of claim 21 further comprising a passive device over said glass substrate.

29. The circuit component of claim 21 further comprising a resistor over said glass substrate.

31. The circuit component of claim 21 further comprising a capacitor over said glass substrate.

32. The circuit component of claim 21 further comprising an inductor over said glass substrate.

33. The circuit component of claim 21 further comprising a spiral-shaped inductor over said glass substrate.

34. The circuit component of claim 21 further comprising a wave guide over said glass substrate.

35. The circuit component of claim 21 further comprising a filter over said glass substrate.

36. The circuit component of claim 21 further comprising a micro electronic mechanical sensor (MEMS) over said glass substrate.

37. The circuit component of claim 21 further comprising a dielectric layer over said glass substrate and said first interconnecting structure.

38. The circuit component of claim 21 further comprising a dielectric layer over said glass substrate and said first interconnecting structure and a second interconnecting structure over said dielectric layer, wherein said second interconnecting structure is connected to said first interconnecting structure through a second opening in said dielectric layer.

39. The circuit component of claim 21 further comprising a gold bump over said glass substrate.

40. The circuit component of claim 21 further comprising a solder bump over said glass substrate.

41. The circuit component of claim 21, wherein said first opening is laser-formed.

42. The circuit component of claim 21, wherein said first interconnecting structure further comprising a third portion vertically over said glass substrate, but not vertically over said die, wherein said third portion is connected to said first portion through said second portion.

43. A chip package comprising:

a glass substrate, wherein a first opening in said glass substrate passes vertically through said glass substrate;

a die comprising multiple active devices;

a first interconnecting structure comprising a first portion in said first opening and a second portion over said glass substrate, wherein said second portion is connected to said die through said first portion; and

a passive device over said glass substrate, wherein said passive device comprises a comb-shaped capacitor.

44. The chip package of claim 43, wherein said die is under said glass substrate.

45. The chip package of claim 43, wherein said glass substrate has a thickness between 2 and 200 micrometers.

46. The chip package of claim 43, wherein said glass substrate has a width greater than that of said die.

47. The chip package of claim 43, wherein said first interconnecting structure comprises copper.

48. The chip package of claim 43, wherein said first interconnecting structure comprises electroplated copper.

49. The chip package of claim 43 further comprising a dielectric layer over said glass substrate and said first interconnecting structure.

50. The chip package of claim 43 further comprising a dielectric layer over said glass substrate and said first interconnecting structure and a second interconnecting structure over said dielectric layer, wherein said second interconnecting structure is connected to said first interconnecting structure through a second opening in said dielectric layer.

51. The chip package of claim 43 further comprising a gold bump over said glass substrate.

52. The chip package of claim 43 further comprising a solder bump over said glass substrate.

53. The chip package of claim 43, wherein said first opening is laser-formed.

54. The chip package of claim 43, wherein said first interconnecting structure further comprising a third portion vertically over said glass substrate, but not vertically in line with said die, wherein said third portion is connected to said first portion through said second portion.