SEMICONDUCTOR MEMORY DEVICE, DRIVING METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
First Claim
1. A matrix-type semiconductor memory device comprising:
- a first line;
a second line;
a third line;
a fourth line; and
a plurality of memory cells,wherein the first line is parallel to the second line,wherein the third line is parallel to the fourth line,wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor,wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor,wherein a gate of the first transistor is connected to the first line,wherein a source of the first transistor and a source of the second transistor are connected to the third line,wherein a drain of the second transistor is connected to the fourth line,wherein the other electrode of the capacitor is connected to the second line, andwherein the third line is provided between the first line and the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. The other electrode of the capacitor is connected to a reading word line. In order to decrease the number of wirings, the writing bit line is substituted for the reading bit line. The reading bit line is formed so as to be embedded in a groove-like opening formed over a substrate.
-
Citations
26 Claims
-
1. A matrix-type semiconductor memory device comprising:
-
a first line; a second line; a third line; a fourth line; and a plurality of memory cells, wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, and wherein the third line is provided between the first line and the substrate. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A matrix-type semiconductor memory device comprising:
-
a first line; a second line; a third line; a fourth line; and a plurality of memory cells, wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, wherein the third line is provided between the first line and the substrate, and wherein the gate of the second transistor is in contact with a semiconductor layer of the first transistor. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A matrix-type semiconductor memory device comprising:
-
a first line; a second line; a third line; a fourth line; and a plurality of memory cells, wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, wherein the third line is provided between the first line and the substrate, and wherein the third line is in contact with a semiconductor layer of the first transistor. - View Dependent Claims (14, 15, 16, 17, 18)
-
-
19. A matrix-type semiconductor memory device comprising:
-
a first line; a second line; a third line; a fourth line; and a plurality of memory cells, wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, wherein the third line is provided between the first line and the substrate, wherein the gate of the second transistor is in contact with a semiconductor layer of the first transistor, and wherein the third line is in contact with the semiconductor layer of the first transistor. - View Dependent Claims (20, 21, 22, 23, 24)
-
-
25. A method for driving a matrix-type semiconductor memory device including a first line, a second line, a third line, a fourth line, and a plurality of memory cells,
wherein the first line is parallel to the second line, wherein the third line is parallel to the fourth line, wherein at least one of the plurality of memory cells includes a first transistor, a second transistor, and a capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the capacitor, wherein a gate of the first transistor is connected to the first line, wherein a source of the first transistor and a source of the second transistor are connected to the third line, wherein a drain of the second transistor is connected to the fourth line, wherein the other electrode of the capacitor is connected to the second line, and wherein the third line is provided between the first line and the substrate. wherein potential of the fourth line is higher than potential of the third line at the time of writing data.
-
26. A method for manufacturing a semiconductor device comprising the steps of:
-
forming a first gate insulating film over a substrate; forming a first line over the first gate insulating film; forming a groove-like opening not in contact with the first line; depositing a conductive material in the groove-like opening; planarizing the conductive material by etching to form a second line; forming a semiconductor layer in contact with the first line and the second line; and forming a second gate insulating film over the semiconductor layer.
-
Specification