SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE

• US 20110205785A1
• Filed: 02/15/2011
• Published: 08/25/2011
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KATO, Kiyoshi, NAGATSUKA, Shuhei, MATSUZAKI, Takanori, INOUE, Hiroki
• Granted Patent: US 8,441,841 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device includes a potential conversion circuit which functions to output a potential lower than a reference potential for reading data from the memory cell. With the use of a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and capable of holding data for a long time can be provided.

Claims

1. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a source line;

a signal line;

a memory cell array including a plurality of memory cells;

a first driver circuit;

a second driver circuit; and

a potential conversion circuit,

wherein one of the plurality of memory cells comprises;

a first transistor including a first gate, a first source, a first drain, and a first channel formation region;

a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and

a capacitor,

wherein the first channel formation region comprises a semiconductor material containing silicon, and the second channel formation region comprises an oxide semiconductor material,

wherein the first gate is electrically connected to one of two electrodes of the capacitor and one of the second source and the second drain,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of the first drain and the first source through the bit line and electrically connected to the other of the second drain and the second source through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to the second gate through the write word line, and

wherein the potential conversion circuit outputs a potential lower than a reference potential to the second driver circuit.

4. The semiconductor device according to claim 1, wherein the plurality of memory cells is connected in parallel between the bit line and the source line.

9. The semiconductor device according to claim 1, wherein the first driver circuit comprises a delay circuit electrically connected to the signal line.

12. The semiconductor device according to claim 1, wherein the second driver circuit includes a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.

2. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a source line;

a signal line;

a memory cell array including a plurality of memory cells;

a first driver circuit;

a second driver circuit; and

a potential conversion circuit,

wherein one of the plurality of memory cells comprises;

a first transistor including a first gate, a first source, a first drain, and a first channel formation region;

a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and

a capacitor,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the first gate is electrically connected to one of two electrodes of the capacitor and one of the second source and the second drain,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of the first drain and the first source through the bit line and electrically connected to the other of the second drain and the second source through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to the second gate through the write word line, and

wherein the potential conversion circuit outputs a potential lower than a reference potential to the second driver circuit.

5. The semiconductor device according to claim 2, wherein the plurality of memory cells is connected in parallel between the bit line and the source line.

7. The semiconductor device according to claim 2, wherein the second channel formation region of the second transistor includes an oxide semiconductor.

10. The semiconductor device according to claim 2, wherein the first driver circuit comprises a delay circuit electrically connected to the signal line.

13. The semiconductor device according to claim 2, wherein the second driver circuit includes a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.

3. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a source line;

a signal line;

a memory cell array including a plurality of memory cells;

a first driver circuit;

a second driver circuit; and

a potential conversion circuit,

wherein one of the plurality of memory cells comprises;

a first transistor including a first gate, a first source, a first drain, and a first channel formation region;

a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and

a capacitor,

wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region,

wherein the first gate is electrically connected to one of two electrodes of the capacitor and one of the second drain and the second source,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of the first drain and the first source through the bit line and electrically connected to the other of the second drain and the second source through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to the second gate through the write word line, and

wherein the potential conversion circuit outputs a potential lower than a reference potential and a potential higher than a power supply potential to the second driver circuit.

6. The semiconductor device according to claim 3, wherein the plurality of memory cells is connected in parallel between the bit line and the source line.

8. The semiconductor device according to claim 3, wherein the second channel formation region of the second transistor includes an oxide semiconductor.

11. The semiconductor device according to claim 3, wherein the first driver circuit comprises a delay circuit electrically connected to the signal line.

14. The semiconductor device according to claim 3, wherein the second driver circuit includes a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.