TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS

• US 20110205791A1
• Filed: 05/05/2011
• Published: 08/25/2011
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Taylor, Jennifer E.
• Granted Patent: US 8,559,218 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

Claims

1. A memory device, comprising:

a table with an output that is used to create a multiplication factor applied to a current to change the magnitude of the current and to compensate for temperature changes in the memory device;

wherein the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

2. The device of claim 1, wherein the operating temperature of the memory device is input to the table to at least partially select the output from a number of possible outputs.

3. The device of claim 1, where the output is supplied to one of an adder and a subtractor that outputs the multiplication factor.

4. The device of claim 1, wherein the multiplication factor is input to a binary weighted current mirror that is supplied with and multiplies a bandgap current.

5. The device of claim 1, wherein the table is a read only memory (ROM) that is placed in an area on a side of a die and is physically segmented to allow for portions of the ROM to be placed in various portions of the area of the die.

6. The device of claim 1, including one or more groups of sets of fuses to generate the current and mirror the current to a number of locations on the memory device.

7. A memory device, comprising:

circuitry including one or more groups of sets of fuses to generate a reference current and mirror the reference current to a number of locations on the memory device; and

a table, wherein the table is used to interpolate an output that is part of a multiplication factor used to change the magnitude of the reference current to compensate for temperature changes in the memory device.

8. The device of claim 7, wherein the table stores data corresponding to a number of reference currents at a number of temperatures.

9. The device of claim 7, where a table output corresponds to a change in magnitude of the reference current from the reference current at a lowest specified operating temperature based on an output from the one or more group of sets of fuses and an output of a temperature sensor.

10. The device of claim 7, including a multiplexor configured to select one of the one or more sets of fuses.

11. The device of claim 7, wherein the memory device includes a number of memory cells, and wherein at least one memory cell is a phase change random access memory (PCRAM) cell.

12. The device of claim 11, wherein the PCRAM cell includes a Germanium-Antimony-Tellurium (GST) material.

13. A memory device, comprising:

a first group of sets of fuses, where each set of fuses has an output corresponding to a respective one of a plurality of reference currents at one of a lowest specified operating temperature and a highest specified operating temperature of the memory device; and

a second group of sets of fuses, where each set of fuses of the second group has an output corresponding to a difference in magnitude between a respective one of the reference currents at the lowest specified operating temperature and at the highest specified operating temperature of the memory device.

14. The device of claim 13, including a temperature sensor, where the temperature sensor has an output corresponding to an operating temperature of the memory device.

15. The device of claim 14, including a table populated with data that corresponds to changes in magnitude of the reference currents at various temperatures, where a table output corresponds to a change in magnitude from a selected one of the reference currents at the one of the lowest specified operating temperature and the highest specified operating temperature to the selected one of the reference currents at the operating temperature based on the output from the second group of sets of fuses and the output of the temperature sensor.

16. The device of claim 15, including one of an adder and a subtractor, where the table output and the output of the first group of sets of fuses are one of added or subtracted to produce a signal corresponding to a magnitude of the selected one of the reference currents at the operating temperature, wherein the signal corresponding to the magnitude of the selected one of the reference currents at the operating temperature is used to produce a reference current having the magnitude and that is used in sensing a state of a memory cell.

17. The device of claim 13, including a multiplexor configured to select one of the sets of fuses from the first group.

18. The device of claim 13, including a multiplexor configured to select one of the sets of fuses from the second group.

19. The device of claim 13, wherein the table comprises a number of single transistor pulldowns.

20. The device of claim 13, wherein the sets of fuses are fuses of a different type than the memory cell.