NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME

• US 20110205802A1
• Filed: 02/17/2011
• Published: 08/25/2011
• Est. Priority Date: 02/22/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOE, Byeong-In, Kang, Changseok, Chang, Sung-Il
• Application Number:
  US13/029,947
• Publication Number:
  US 20110205802A1
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.

Claims

1. A nonvolatile memory device comprising:

a memory cell;

a transistor disposed between a common source line and the memory cell; and

a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation.

2. The nonvolatile memory device of claim 1, wherein the transistor operates in a triode state according to the bias voltage.

3. The nonvolatile memory device of claim 1, wherein the bias voltage applied to the transistor is higher than a bias voltage applied to the memory cell.

4. The nonvolatile memory device of claim 1, further comprising a plurality of memory cells disposed between a bit line and the common source line and connected in series to the memory cell.

5. A nonvolatile memory device comprising:

a plurality of memory cells connected in series;

a transistor between a common source line and the plurality of memory cells; and

a control logic for controlling bias voltages applied to the plurality of memory cells and the transistor,

wherein the control logic controls a non-select read voltage applied to an unselected memory cell among the plurality of memory cells and a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation.

6. The nonvolatile memory device of claim 5, wherein the bias voltage of the transistor is higher than a ground voltage and is lower than the non-select read voltage.

7. The nonvolatile memory device of claim 5, wherein the bias voltage of the transistor is higher than a bias voltage applied to a selected memory cell among the plurality of memory cells.

8. The nonvolatile memory device of claim 5, wherein the control logic controls a select read voltage applied to a selected memory cell among the plurality of memory cells.

9. The nonvolatile memory device of claim 8, wherein the select read voltage is a read voltage for determining one of an erase state and a program state of the selected memory cell.

10. The nonvolatile memory device of claim 8, wherein the select read voltage is a program verify voltage for determining a program state of the selected memory cell.

11. The nonvolatile memory device of claim 8, wherein the non-select read voltage is higher than the select read voltage.

12. The nonvolatile memory device of claim 5, wherein the transistor has the same structure as the memory cell.

13. The nonvolatile memory device of claim 12, wherein the transistor is programmed before a read operation or a program operation is performed.

14. The nonvolatile memory device of claim 13, wherein a threshold voltage of the transistor is higher than a select read voltage applied to a selected memory cell among the plurality of memory cells and is lower than the non-select read voltage.

15. The nonvolatile memory device of claim 13, wherein the non-select read voltage is the same as a bias voltage of the transistor.

16. The nonvolatile memory device of claim 5, wherein:

a first non-select read voltage is applied to a first unselected memory cell connected to between a selected memory cell among the plurality of memory cells and the common source line;

a second non-select read voltage is applied to a second unselected memory cell connected to between the selected memory cell and the bit line; and

the first non-select read voltage is higher than a ground voltage and is lower than the second non-select read voltage.

17. The nonvolatile memory device of claim 16, wherein the first non-select read voltage is higher than a bias voltage applied to the selected memory cell.

18. A method of reading a nonvolatile memory device including a memory cell and a transistor between a common source line and the memory cell, the method comprising:

applying a read voltage to the memory cell; and

controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.

19. The method of claim 18, wherein the bias voltage of the transistor is higher than the read voltage.

20. The method of claim 18, wherein the transistor comprises a memory cell transistor having the same structure as the memory cell and the method further includes programming the memory cell transistor before the read voltage is applied.