MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS

• US 20110208893A1
• Filed: 04/15/2011
• Published: 08/25/2011
• Est. Priority Date: 05/14/1999
• Status: Active Grant

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis LLC (Acqis Technology, Inc.)
• Inventors: Chu, William W.Y.
• Granted Patent: US 8,234,436 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Claims

1-43. -43. (canceled)

44. A computer system comprising:

a processing unit;

a peripheral bridge to communicate serial bits of Peripheral Component Interconnect (PCI) bus transaction, the peripheral bridge directly coupled to the processing unit;

a low voltage differential signal (LVDS) channel comprising at least two unidirectional, differential signal pairs to convey data in opposite directions, the LVDS channel extending from the peripheral bridge to convey the serial bits of PCI bus transaction, the serial bits of PCI bus transaction comprising PCI address and data bits;

a main memory coupled to the processing unit through the peripheral bridge; and

a peripheral component coupled to the peripheral bridge.

45. The computer system of claim 44, wherein the peripheral component is coupled to the peripheral bridge through the LVDS channel.

46. The computer system of claim 45, wherein the peripheral component is coupled to the processing unit through the LVDS channel and the peripheral bridge.

47. The computer system of claim 45, wherein the peripheral component comprises a serial communication controller.

48. The computer system of claim 44, further comprising a graphics subsystem coupled to the processing unit through the peripheral bridge.

49. The computer system of claim 44, wherein the peripheral bridge comprises a north bridge.

50. The computer system of claim 49, wherein the peripheral bridge comprises an interface controller integrated with the north bridge, the interface controller is coupled to the processing unit without any intervening PCI bus, and the interface controller is configured to output encoded address and data bits of PCI bus transaction in serial form that are conveyed over the LVDS channel.

51. The computer system of claim 44, wherein the serial bits of PCI bus transaction comprise information to permit decoding to create a PCI bus transaction.

52. The computer system of claim 44, wherein the LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.

53. A computer system comprising:

a computer module insertable into a console for operation, the computer module comprising

a processing unit,

an integrated interface controller and bridge unit to output encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form, the integrated interface controller and bridge unit coupled to the processing unit without any intervening PCI bus,

a low voltage differential signal (LVDS) channel coupled to the integrated interface controller and bridge unit to convey the encoded address and data bits of PCI bus transaction in serial form, and

a main memory coupled to the processing unit through the integrated interface controller and bridge unit.

54. The computer system of claim 53, further comprising a peripheral component coupled to the integrated interface controller and bridge unit through the LVDS channel.

55. The computer system of claim 53, wherein the LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.

56. The computer system of claim 53, wherein the integrated interface controller and bridge unit comprises a north bridge and an interface controller integrated with the north bridge.

57. The computer system of claim 53, wherein the computer module comprises an enclosure housing the processing unit, the integrated interface controller and bridge unit, the LVDS channel, and the main memory.

58. The computer system of claim 53, further comprising the console, and the console comprises a power supply to supply power to the computer module upon insertion into the console.

59. The computer system of claim 58, wherein the console comprises a coupling site and a multi-port, serial communication hub controller, and the computer module comprises a serial communication controller to communicate, via a point-to-point link, with the multi-port, serial communication hub controller through the coupling site of the console.

60. A computer system comprising:

a processing unit;

a low voltage differential signal (LVDS) channel comprising at least two unidirectional serial bit channels to convey data in opposite directions;

a north bridge coupled to the processing unit, the north bridge comprising an interface controller to transmit and receive serial bits of Peripheral Component Interconnect (PCI) bus transaction over the LVDS channel;

a main memory coupled to the processing unit through the north bridge; and

a south bridge coupled to the processing unit through the north bridge.

61. The computer system of claim 60, wherein the south bridge is coupled to the north bridge through the LVDS channel.

62. The computer system of claim 61, further comprising a peripheral component coupled to the processing unit through the south bridge, the LVDS channel, and the north bridge.

63. The computer system of claim 60, wherein the north bridge is directly coupled to the processing unit.

64. The computer system of claim 60, wherein the north bridge and the interface controller are coupled to the processing unit without any intervening PCI bus, and the interface controller is integrated with the north bridge.

65. The computer system of claim 60, wherein the serial bits of PCI bus transaction comprise encoded PCI address and data bits, the LVDS channel extends from the north bridge to convey the encoded PCI address and data bits, and the LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.

66. A computer system comprising:

a processing unit;

a main memory coupled to the processing unit;

a first low voltage differential signal (LVDS) channel comprising at least two unidirectional serial bit channels to convey data in opposite directions;

a first peripheral bridge coupled to the processing unit without any intervening Peripheral Component Interconnect (PCI) bus, the first peripheral bridge coupled to the first LVDS channel to communicate address and data information of PCI bus transaction in serial form over the first LVDS channel; and

a second peripheral bridge coupled to the first peripheral bridge.

67. The computer system of claim 66, wherein the main memory is coupled to the processing unit through the first peripheral bridge.

68. The computer system of claim 66, wherein the second peripheral bridge is coupled to the first peripheral bridge through the first LVDS channel.

69. The computer system of claim 66, wherein the first LVDS channel comprises two sets of unidirectional, multiple serial bit channels to convey data in opposite directions.

70. The computer system of claim 66, further comprising a mass storage device coupled to the second peripheral bridge.

71. The computer system of claim 66, further comprising a second LVDS channel comprising at least two unidirectional serial bit channels to convey data in opposite directions, and the second peripheral bridge is coupled to the second LVDS channel to communicate PCI bus transaction in serial form over the second LVDS channel.

72. The computer system of claim 66, wherein the first peripheral bridge comprises a north bridge, and the second peripheral bridge comprises a south bridge.

73. The computer system of claim 72, wherein the first peripheral bridge comprises an interface controller integrated with the north bridge, the interface controller is configured to output an encoded serial bit stream of PCI bus transaction, and the first LVDS channel extends from the interface controller to convey the encoded serial bit stream of PCI bus transaction.

74. A computer module comprising:

an enclosure insertable into a console;

a processing unit housed in the enclosure, the processing unit comprising an interface controller to transmit and receive serial bits of Peripheral Component Interconnect (PCI) bus transaction, the serial bits of PCI bus transaction comprising PCI address and data bits;

a system memory housed in the enclosure and directly coupled to the processing unit; and

a low voltage differential signal (LVDS) channel housed in the enclosure, the LVDS channel comprising a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction, the LVDS channel extending from the processing unit to convey the serial bits of PCI bus transaction.

75. The computer module of claim 74, wherein the processing unit and interface controller are integrated in a single chip.

76. The computer module of claim 75, wherein the processing unit comprises a graphics subsystem integrated in the single chip.

77. The computer module of claim 76, further comprising a graphics memory directly coupled to the processing unit.

78. The computer module of claim 74, further comprising a mass storage device directly coupled to the processing unit.

79. The computer module of claim 74, wherein the interface controller is configured to output encoded address and data bits of PCI bus transaction in serial form that are conveyed over the LVDS channel.

80. The computer module of claim 74, wherein the LVDS channel comprises a third unidirectional, differential signal pair to convey data in the first direction and a fourth unidirectional, differential signal pair to convey data in the second, opposite direction.

81. The computer module of claim 74, wherein the computer module is configured to operate only upon receiving power from the console.

82. The computer module of claim 74, wherein the enclosure defines a set of grooves to engage a corresponding set of rails of the console.

83. A computer system comprising:

a computer module comprising

an enclosure insertable into a console,

an integrated interface controller and processing unit to output encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form, the integrated interface controller and processing unit configured as a single chip and housed in the enclosure,

a low voltage differential signal (LVDS) channel housed in the enclosure, the LVDS channel coupled to the integrated interface controller and processing unit to convey the encoded address and data bits of PCI bus transaction in serial form, and

a system memory housed in the enclosure and coupled to the integrated interface controller and processing unit.

84. The computer system of claim 83, wherein the integrated interface controller and processing unit comprises a graphics subsystem integrated in the single chip.

85. The computer system of claim 84, further comprising the console, and the console comprises a LCD display coupled to the graphics subsystem.

86. The computer system of claim 83, further comprising a peripheral component coupled to the integrated interface controller and processing unit through the LVDS channel.

87. The computer system of claim 83, wherein the LVDS channel comprises a first plurality of unidirectional, differential signal pairs to convey data in a first direction and a second plurality of unidirectional, differential signal pairs to convey data in a second, opposite direction.

88. The computer system of claim 83, further comprising the console, and the console comprises a power supply to supply power to the computer module upon insertion into the console.

89. The computer system of claim 88, wherein the console comprises a coupling site and a multi-port, Ethernet hub controller, and the computer module comprises an Ethernet controller to communicate, via a point-to-point Ethernet link, with the multi-port, Ethernet hub controller through the coupling site of the console.

90. A computer system comprising:

a low voltage differential signal (LVDS) channel comprising at least two unidirectional serial bit channels to convey data in opposite directions;

a processing unit comprising an interface coupled to the LVDS channel to communicate PCI bus transaction in serial form over the LVDS channel;

a system memory directly coupled to the processing unit; and

a peripheral component coupled to the processing unit through the LVDS channel.

91. The computer system of claim 90, wherein the processing unit comprises a graphics subsystem integrated with the processing unit in a single chip.

92. The computer system of claim 91, further comprising a graphics memory directly coupled to the processing unit.

93. The computer system of claim 90, further comprising a mass storage device directly coupled to the processing unit.

94. The computer system of claim 90, wherein the peripheral component comprises a serial communication controller.

95. The computer system of claim 90, wherein the LVDS channel comprises two sets of unidirectional, multiple serial bit channels to convey data in opposite directions.

96. The computer system of claim 90, wherein the interface of the processing unit is configured to output an encoded serial bit stream of PCI address and data information, and the LVDS channel extends from the interface of the processing unit to convey the encoded serial bit stream.