Memory Systems and Methods of Operating the Same

• US 20110208901A1
• Filed: 02/25/2011
• Published: 08/25/2011
• Est. Priority Date: 02/25/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jung Wook, Jeon, Taekeun, Choi, Chang-Eun, Kim, Hyun-Ju, Bae, Kyoungryun
• Granted Patent: US 8,892,842 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory system includes a nonvolatile memory device, a memory controller for controlling the nonvolatile memory device and a virtual data interface layer that manages reading and/or writing of patterned data from/to the nonvolatile memory device. In a read operation, the virtual data interface layer generates patterned data that is requested to be read. Accordingly, a read speed of the memory system may be improved.

Claims

1. A memory system, comprising:

a nonvolatile memory device; and

a memory controller coupled to the nonvolatile memory device and configured to manage patterned data that is received by the memory system for storage in the nonvolatile memory, the patterned data comprising repeated occurrences of a data pattern, wherein the memory controller is configured, in response to a read request for the patterned data, to generate the patterned data responsive to the stored data pattern.

2. The memory system of claim 1, wherein the memory controller comprises a virtual data interface layer that manages a data pattern table in which the data pattern and an address corresponding to the data pattern are stored.

3. The memory system of claim 1, wherein the virtual data interface layer comprises:

a data analysis module configured to determine whether or not an address requested to be read corresponds to the address stored in the data pattern table; and

a data generation module configured to generate the patterned data corresponding to the address requested to be read with reference to the data pattern stored in the data pattern table.

4. The memory system of claim 2, wherein the memory controller comprises a random access memory, and wherein the data generation module is configured to store the generated patterned data in the random access memory.

5. The memory system of claim 1, wherein the virtual data interface layer comprises:

a data analysis module configured to determine whether or not data received by the memory controller is patterned data; and

a data pool module configured to store a data pattern of the data received by the memory controller and an address corresponding to the data received by the memory controller in the data pattern table.

6. The memory system of claim 4, wherein the data analysis module comprises:

a first buffer configured to store first data parsed from the received data; and

a second buffer configured to store second data parsed from the received data.

7. The memory system of claim 5, wherein the data analysis module is configured to compare the first data stored in the first buffer with the second data stored in the second buffer to determine whether the first and second data comprise patterned data or not.

8. The memory system of claim 4, wherein the data pool module is configured to store the data pattern table in a random access memory of the memory controller.

9. The memory system of claim 1, wherein the virtual data interface layer is configured to transmit the address requested to be read to the nonvolatile memory device in the case that the address requested to be read is not an address stored in the data pattern table.

10. The memory system of claim 1, wherein the nonvolatile memory device comprises a flash memory that comprises a flash translation layer configured to manage an address mapping operation between the flash memory and a host, and wherein the virtual data interface layer is configured to generate clean data in the case that the address requested to be read is not an address stored in the data pattern table or the flash translation layer.

11. A method of operating a memory system wherein the memory system comprises a data pattern table comprising a data pattern and an address corresponding to the data pattern, the method comprising:

receiving an address from which data is requested to be read;

determining whether or not the address requested to be read corresponds to the address stored in the data pattern table; and

generating patterned data corresponding to the address requested to be read in response to the corresponding data pattern in the data pattern table.

12. The method of claim 11, wherein the memory system comprises a nonvolatile memory device and a memory controller for controlling the nonvolatile memory device, and wherein the data pattern table is stored in a random access memory of the memory controller.

13. The method of claim 12, wherein the nonvolatile memory device comprises a first nonvolatile memory device, and wherein the data pattern table is stored in a second nonvolatile memory device inside the memory controller at regular intervals and/or during an idle time.

14. The method of claim 12, wherein in the case that the address requested to be read does not correspond to the address stored in the data pattern table, a read operation is performed on the nonvolatile memory device.

15. The method of claim 11, wherein the memory system comprises a flash memory and a flash translation layer for managing an address mapping operation between the host and the flash memory device.

16. The method of claim 15, further comprising generating clean data in the case that the address requested to be read does not correspond to an address stored in the data pattern table or the flash translation layer.

17. A method of operating a memory system wherein the memory system comprises a data pattern table for managing data received by the memory system, the method comprising:

receiving an address at which received data is to be written;

determining whether or not the received data is patterned data; and

in response to the received data being patterned data, registering a data pattern of the patterned data and an address corresponding to the data pattern in the data pattern table.

18. The method of claim 17, wherein determining whether or not the received data is patterned data comprises storing first and second sub data parsed from the received data in first and second buffers, respectively and comparing the first sub data stored in the first buffer with the second sub data stored in the second buffer.

19. The method of claim 18, wherein the memory system comprises a nonvolatile memory device and a memory controller controlling the nonvolatile memory device, wherein in the case that the received data is not patterned data, the received data is programmed into the nonvolatile memory device.

20. The method of claim 19, wherein the data pattern table is stored in a random access memory of the memory controller.

21-22. -22. (canceled)