PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

• US 20110208925A1
• Filed: 08/23/2010
• Published: 08/25/2011
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Ajay Bhatt, Anil Vasudevan, Avi Mendelson, David Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Original Assignee: Ajay Bhatt, Anil Vasudevan, Avi Mendelson, David Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Inventors: Bhatt, Ajay, Muthrasanallur, Sridhar, Shamia, Doron, Barry, Peter, Wagh, Mahesh, Blankenship, Robert, Sharma, Debendra Das, Ajanovic, Jasmin, Sethi, Prashant, Pardo, Ilan, Harriman, David, Mendelson, Avi (Abraham), Rodgers, Scott Dion, Rosenbluth, Mark, Akiyama, James, Falik, Ohad, Vasudevan, Anil, Weissmann, Eliezer, Tamari, Eran
• Granted Patent: US 8,230,119 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. A system comprising:

a device including a first input/output (I/O) module comprising a protocol stack to transmit a request packet, the request packet to include a first field to specify an atomic operation; and

a controller hub coupled to the device through a serial point-to-point interconnect including;

a second input/output (I/O) module including a protocol stack to receive the request packet on the serial point to point interconnect,

decode logic coupled to the I/O module to decode the first field and to detect the atomic operation, and

logic to service the atomic operation in response to detecting the atomic operation.

2. The system of claim 1, wherein the first field includes a predetermined bit pattern to specify the atomic operation, and wherein the decode logic to decode the first field and to detect the atomic operation includes the decode logic detecting the predetermined bit pattern in the first field of the request packet.

3. The system of claim 1, wherein the logic to service the atomic operation includes read modify write (RMW) logic to initiate:

a read of an old value from a memory location in a memory device coupled to the controller hub, the memory location being associated with the atomic operation,

a modification of the old value to a Previously Added value, and

a write of the Previously Added value to the memory location.

4. The system of claim 3, wherein the request packet also includes an identifier associated with the atomic operation, and wherein the RMW logic is also to transmit a response packet on the serial point-to-point interconnect to the device in response to the RMW logic servicing the atomic operation, the response packet to include the identifier and the old value.

5. A method comprising:

receiving a first request packet with a controller hub utilizing a layered protocol stack, the first request packet to include a first field, wherein the first field is to include a reference to an atomic operation;

servicing the atomic operation with the controller hub; and

generating a response message in response to servicing the atomic operation.

6. The method of claim 5, wherein the first request packet is also to include a unique identifier.

7. The method of claim 6, further comprising:

generating the first request packet with a device selected from a group consisting of an accelerator, an I/O device, and a network interface controller (NIC).

8. The method of claim 6, wherein the atomic operation is selected from a group consisting of BitSet, BitClear, Two'"'"'s Complement Add, Swap, and Test &

Swap.

9. The method of claim 6, wherein servicing the atomic operation includes:

reading an initial value stored in a memory location referenced in the first request packet;

writing a second value referenced to the memory location.

10. The method of claim 9, wherein the response message is to include the unique identifier and the initial value.

11. A method comprising:

generating a request packet with a device, the request packet including a reference to an atomic operation and a packet identifier;

storing an outstanding reference to the request packet in the device, the outstanding reference including a reference to the packet identifier;

transmitting the request packet over a point-to-point, coherent fabric to a controller utilizing a layered protocol stack; and

retiring the outstanding reference to the request packet stored in the device in response to receiving a response message with the device from the controller.

12. The method of claim 11, further comprising

receiving the request packet with the controller;

determining the atomic operation from the request packet in response to receiving the request packet with the controller;

servicing the atomic operation in response to determining the atomic operation from the request packet;

transmitting a response message in response to servicing the atomic operation, the response message including the reference to the packet identifier

13. The method of claim 11, wherein the atomic operation includes a read, modify, write (RMW) operation, and wherein the RMW operation is selected from a group consisting of:

BitSet, BitClear, Two'"'"'s Complement Add, Swap, and Test &

Swap.

14. An apparatus comprising:

an integrated circuit including,

a protocol stack including layered protocol stack adapted to assemble a request packet to include a reference to an atomic operation and a packet identifier;

outstanding logic adapted to hold an outstanding reference to the request packet, the outstanding reference including a reference to the packet identifier;

the layered protocol stack adapted to transmit the request packet over a point-to-point, coherent fabric to a controller; and

retirement logic adapted to retire the outstanding reference to the request packet from the outstanding logic in response to receiving a response message from the controller.

15. The apparatus of claim 14, further comprising:

the controller adapted to be coupled to the integrated circuit, the controller including,

a layered protocol stack adapted to receive the request packet and to determine the atomic operation from the request packet in response to receiving the request packet;

logic to service the atomic operation in response to determining the atomic operation from the request packet;

wherein the layered protocol stack is further adapted to transmit the response message in response to the logic servicing the atomic operation, the response message including the reference to the packet identifier

16. The apparatus of claim 14, wherein the atomic operation includes a read, modify, write (RMW) operation, and wherein the RMW operation is selected from a group consisting of:

BitSet, BitClear, Two'"'"'s Complement Add, Swap, and Test &

Swap.