SEMICONDUCTOR DEVICE

• US 20110210326A1
• Filed: 02/17/2011
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SUZAWA, Hideomi, SASAGAWA, Shinya, KURATA, Motomu
• Granted Patent: US 8,653,513 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a source electrode comprising;

a first conductive layer; and

a second conductive layer in contact with the semiconductor layer;

a drain electrode comprising;

a third conductive layer; and

a fourth conductive layer in contact with the semiconductor layer;

a first sidewall insulating layer in contact with the source electrode;

a second sidewall insulating layer in contact with the drain electrode;

a gate electrode overlapping with the semiconductor layer; and

a gate insulating layer between the semiconductor layer and the gate electrode,

wherein the second conductive layer has a first region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode,

wherein the fourth conductive layer has a second region which extends beyond an end portion of the third conductive layer in the channel length direction and which overlaps with part of the gate electrode,

wherein the first sidewall insulating layer is provided on the first region,

wherein the second sidewall insulating layer is provided on the second region, and

wherein the first sidewall insulating layer and the second sidewall insulating layer each comprise a stack of a plurality of different material layers.

2. The semiconductor device according to claim 1,

wherein the stack of the plurality of different material layers comprises a stack of a nitride insulating layer and an oxide insulating layer.

3. The semiconductor device according to claim 2,

wherein the oxide insulating layer is provided over the nitride insulating layer.

4. The semiconductor device according to claim 2,

wherein the nitride insulating layer comprises silicon nitride, silicon nitride oxide, or aluminum nitride, and

wherein the oxide insulating layer comprises silicon oxide, silicon oxynitride, or aluminum oxide.

5. The semiconductor device according to claim 1,

wherein the first conductive layer and the second conductive layer each have a tapered shape, and

wherein the third conductive layer and the fourth conductive layer each have a tapered shape.

6. The semiconductor device according to claim 1,

wherein the second conductive layer and the fourth conductive layer each comprise nitride of a metal.

7. The semiconductor device according to claim 1,

wherein the second conductive layer and the fourth conductive layer each have a thickness of greater than or equal to 5 nm and less than or equal to 15 nm.

8. The semiconductor device according to claim 1, further comprising:

a first insulating layer provided between the semiconductor layer and a top surface of the source electrode; and

a second insulating layer provided between the semiconductor layer and a top surface of the drain electrode,

wherein the source electrode and the drain electrode are in contact with the semiconductor layer at end portions of the source electrode and the drain electrode.

9. The semiconductor device according to claim 1,

wherein the first sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer, and

wherein the second sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer.

10. A semiconductor device comprising:

a semiconductor layer;

a source electrode comprising;

a first conductive layer; and

a second conductive layer in contact with the semiconductor layer;

a drain electrode comprising;

a third conductive layer; and

a fourth conductive layer in contact with the semiconductor layer;

a first sidewall insulating layer in contact with the source electrode;

a second sidewall insulating layer in contact with the drain electrode;

a gate electrode overlapping with the semiconductor layer; and

a gate insulating layer between the semiconductor layer and the gate electrode,

wherein the second conductive layer has a first region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode,

wherein the fourth conductive layer has a second region which extends beyond an end portion of the third conductive layer in the channel length direction and which overlaps with part of the gate electrode,

wherein the first sidewall insulating layer is provided on the first region,

wherein the second sidewall insulating layer is provided on the second region,

wherein the first sidewall insulating layer and the second sidewall insulating layer each comprise a stack of a plurality of different material layers, and

wherein the semiconductor layer is an oxide semiconductor layer.

11. The semiconductor device according to claim 10,

wherein the stack of the plurality of different material layers comprises a stack of a nitride insulating layer and an oxide insulating layer.

12. The semiconductor device according to claim 11,

wherein the oxide insulating layer is provided over the nitride insulating layer.

13. The semiconductor device according to claim 11,

wherein the nitride insulating layer comprises silicon nitride, silicon nitride oxide, or aluminum nitride, and

wherein the oxide insulating layer comprises silicon oxide, silicon oxynitride, or aluminum oxide.

14. The semiconductor device according to claim 10,

wherein the first conductive layer and the second conductive layer each have a tapered shape, and

wherein the third conductive layer and the fourth conductive layer each have a tapered shape.

15. The semiconductor device according to claim 10,

wherein the second conductive layer and the fourth conductive layer each comprise nitride of a metal.

16. The semiconductor device according to claim 10,

wherein the second conductive layer and the fourth conductive layer each have a thickness of greater than or equal to 5 nm and less than or equal to 15 nm.

17. The semiconductor device according to claim 10, further comprising:

a first insulating layer provided between the semiconductor layer and a top surface of the source electrode; and

a second insulating layer provided between the semiconductor layer and a top surface of the drain electrode,

wherein the source electrode and the drain electrode are in contact with the semiconductor layer at end portions of the source electrode and the drain electrode.

18. The semiconductor device according to claim 10,

wherein the first sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer, and

wherein the second sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer.

19. A semiconductor device comprising:

a semiconductor layer;

a source electrode comprising;

a first conductive layer; and

a second conductive layer in contact with the semiconductor layer;

a drain electrode comprising;

a third conductive layer; and

a fourth conductive layer in contact with the semiconductor layer;

a first sidewall insulating layer in contact with the source electrode;

a second sidewall insulating layer in contact with the drain electrode;

a gate electrode overlapping with the semiconductor layer; and

a gate insulating layer between the semiconductor layer and the gate electrode,

wherein the second conductive layer has a first region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode,

wherein the fourth conductive layer has a second region which extends beyond an end portion of the third conductive layer in the channel length direction and which overlaps with part of the gate electrode,

wherein the first sidewall insulating layer is provided on the first region,

wherein the second sidewall insulating layer is provided on the second region,

wherein the first sidewall insulating layer and the second sidewall insulating layer each comprise a stack of a plurality of different material layers, and

wherein a material included in the second conductive layer has higher resistance than a material included in the first conductive layer.

20. The semiconductor device according to claim 19,

wherein the stack of the plurality of different material layers comprises a stack of a nitride insulating layer and an oxide insulating layer.

21. The semiconductor device according to claim 20,

wherein the oxide insulating layer is provided over the nitride insulating layer.

22. The semiconductor device according to claim 20,

wherein the nitride insulating layer comprises silicon nitride, silicon nitride oxide, or aluminum nitride, and

wherein the oxide insulating layer comprises silicon oxide, silicon oxynitride, or aluminum oxide.

23. The semiconductor device according to claim 19,

wherein the first conductive layer and the second conductive layer each have a tapered shape, and

wherein the third conductive layer and the fourth conductive layer each have a tapered shape.

24. The semiconductor device according to claim 19,

wherein the second conductive layer and the fourth conductive layer each comprise nitride of a metal.

25. The semiconductor device according to claim 19,

wherein the second conductive layer and the fourth conductive layer each have a thickness of greater than or equal to 5 nm and less than or equal to 15 nm.

26. The semiconductor device according to claim 19, further comprising:

a first insulating layer provided between the semiconductor layer and a top surface of the source electrode; and

a second insulating layer provided between the semiconductor layer and a top surface of the drain electrode,

wherein the source electrode and the drain electrode are in contact with the semiconductor layer at end portions of the source electrode and the drain electrode.

27. The semiconductor device according to claim 19,

wherein the first sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer, and

wherein the second sidewall insulating layer is in contact with the semiconductor layer and has a curved surface at least partly in a region in contact with the semiconductor layer.

28. The semiconductor device according to claim 19,

wherein the semiconductor layer is an oxide semiconductor layer.