LIQUID CRYSTAL DISPLAY DEVICE

• US 20110210327A1
• Filed: 02/17/2011
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KONDO, Toshikazu, YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 8,502,226 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

Claims

1. A liquid crystal display device comprising:

a first scan line and a second scan line arranged in parallel or substantially parallel to each other;

a first signal line and a second signal line arranged in parallel or substantially parallel to each other; and

a liquid crystal element surrounded by the first scan line, the second scan line, the first signal line, and the second signal line,

wherein the first signal line intersects with the first scan line so that a first step is formed in the first signal line due to the first scan line,

wherein the first signal line intersects with the second scan line so that a second step is formed in the first signal line due to the second scan line, and

wherein the whole of an upper surface of the first signal line exists coplanarly or substantially coplanarly in a region which is interposed between the first step and the second step.

2. The liquid crystal display device according to claim 1, further comprising a transistor,

wherein the transistor includes an oxide semiconductor layer.

3. The liquid crystal display device according to claim 2,

wherein the oxide semiconductor layer comprises gallium, zinc, and indium.

4. The liquid crystal display device according to claim 2,

wherein the transistor comprises a gate which is electrically connected to the first scan line.

5. The liquid crystal display device according to claim 2,

wherein the transistor comprises a source and a drain,

wherein one of the source and the drain is electrically connected to the first signal line, and

wherein the other of the source and the drain is electrically connected to the liquid crystal element.

6. A liquid crystal display device comprising:

a first scan line and a second scan line arranged in parallel or substantially parallel to each other;

a first signal line and a second signal line arranged in parallel or substantially parallel to each other;

a liquid crystal element surrounded by the first scan line, the second scan line, the first signal line, and the second signal line; and

a transistor including a gate, an insulating layer, a semiconductor layer, a source, and a drain,

wherein the first signal line intersects with the first scan line so that a first step is formed in the first signal line due to the first scan line,

wherein the first signal line intersects with the second scan line so that a second step is formed in the first signal line due to the second scan line, and

wherein the whole of an upper surface of the first signal line exists coplanarly or substantially coplanarly in a region which is interposed between the first step and the second step.

7. The liquid crystal display device according to claim 6,

wherein the insulating layer is further sandwiched between the first signal line and the first scan line and between the first signal line and the second scan line.

8. The liquid crystal display device according to claim 7,

wherein the first signal line is formed over and in contact with the insulating layer.

9. The liquid crystal display device according to claim 6,

wherein the insulating layer and the semiconductor layer are further sandwiched between the first signal line and the first scan line and between the first signal line and the second scan line.

10. The liquid crystal display device according to claim 9,

wherein the first signal line is formed over the insulating layer and the semiconductor layer, and

wherein the first signal line is in contact with the semiconductor layer.

11. The liquid crystal display device according to claim 6,

wherein the semiconductor layer comprises an oxide semiconductor.

12. The liquid crystal display device according to claim 6,

wherein the semiconductor layer comprises gallium, zinc, and indium.

13. A liquid crystal display device comprising a plurality of pixels, at least one of the plurality of pixels comprising:

a scan line;

a signal line;

a transistor comprising a gate, a source, and a drain, wherein the gate is electrically connected to the scan line, and one of the source and the drain is electrically connected to the signal line; and

a liquid crystal element electrically connected to the other of the source and the drain,

wherein the signal line intersects with the scan line so that a step is formed in the signal line due to the scan line, and

wherein the whole of an upper surface of the signal line exists coplanarly or substantially coplanarly in a region between the step and the step which is located in a neighboring pixel.

14. The liquid crystal display device according to claim 13,

wherein the transistor comprises an insulating layer which is in contact with the gate, and

wherein the insulating layer is further sandwiched between the signal line and the scan line.

15. The liquid crystal display device according to claim 14,

wherein the signal line is formed over and in contact with the insulating layer.

16. The liquid crystal display device according to claim 13,

wherein the transistor comprises:

an insulating layer in contact with the gate; and

a semiconductor layer in contact with the insulating layer, and

wherein the insulating layer and the semiconductor layer are sandwiched between the signal line and the scan line.

17. The liquid crystal display device according to claim 16,

wherein the signal line is in contact with the semiconductor layer.

18. The liquid crystal display device according to claim 16,

wherein the signal line is in contact with the insulating layer in the region.

19. The liquid crystal display device according to claim 16,

wherein the signal line is in contact with the semiconductor layer in a second region in which the signal line overlaps with the scan line, and

wherein the signal line is in contact with the insulating layer in the region.

20. The liquid crystal display device according to claim 13,

wherein the transistor comprises an oxide semiconductor layer.

21. The liquid crystal display device according to claim 13,

wherein the transistor comprises an oxide semiconductor layer comprising gallium, zinc, and indium.