SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110210328A1
• Filed: 05/10/2011
• Published: 09/01/2011
• Est. Priority Date: 12/26/2008
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun, SAKATA, Junichiro
• Application Number:
  US13/104,548
• Publication Number:
  US 20110210328A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

Claims

1. A semiconductor device comprising:

a substrate;

a transistor over the substrate, the transistor comprising an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—

Sn—

Zn—

O based semiconductor; and

an insulating layer comprising aluminum oxide over the oxide semiconductor layer.

2. The semiconductor device according to claim 1 wherein the transistor is a bottom-gate n-channel transistor.

3. The semiconductor device according to claim 1 wherein the transistor comprises a source electrode and a drain electrode over the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is amorphous.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains an insulating impurity.

6. A semiconductor device comprising a circuit, the circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,

wherein a gate of the third transistor is electrically connected to the one of the source and the drain of the third transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and

wherein a gate of the eighth transistor is electrically connected to a gate of the fifth transistor,

wherein each of the first, second, third, fourth, fifth, sixth, seventh and eighth transistors comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—

Sn—

Zn—

O based semiconductor.

7. The semiconductor device according to claim 6 wherein each of the first, second, third, fourth, fifth, sixth, seventh and eighth transistors is a bottom-gate n-channel transistor.

8. The semiconductor device according to claim 6 further comprising an insulating film over the oxide semiconductor layer, wherein the insulating film comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and tantalum oxide.

9. The semiconductor device according to claim 6 wherein each of the first, second, third, fourth, fifth, sixth, seventh and eighth transistors comprises a source electrode and a drain electrode formed over the oxide semiconductor layer.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor layer is amorphous.

11. The semiconductor device according to claim 6, wherein the oxide semiconductor layer contains an insulating impurity.

12. A semiconductor device comprising an inverter circuit, the inverter circuit comprising:

a first transistor;

a second transistor;

wherein a source of the first transistor is electrically connected to a drain of the second transistor;

wherein a gate of the first transistor is electrically connected to the source of the first transistor, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—

Sn—

Zn—

O based semiconductor.

13. The semiconductor device according to claim 12 wherein each of the first and second transistors is a bottom-gate n-channel transistor.

14. The semiconductor device according to claim 12 further comprising an insulating film over the oxide semiconductor layer, wherein the insulating film comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and tantalum oxide.

15. The semiconductor device according to claim 12 wherein each of the first and second transistors comprises a source electrode and a drain electrode formed over the oxide semiconductor layer.

16. The semiconductor device according to claim 12, wherein the oxide semiconductor layer is amorphous.

17. The semiconductor device according to claim 12, wherein the oxide semiconductor layer contains an insulating impurity.

18. The semiconductor device according to claim 12 wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

19. A semiconductor device comprising an inverter circuit, the inverter circuit comprising:

a first transistor; and

a second transistor;

wherein a source of the first transistor is electrically connected to a drain of the second transistor;

wherein a gate of the first transistor is electrically connected to a drain of the first transistor, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—

Sn—

Zn—

O based semiconductor.

20. The semiconductor device according to claim 19 wherein each of the first and second transistors is a bottom-gate n-channel transistor.

21. The semiconductor device according to claim 19 further comprising an insulating film over the oxide semiconductor layer, wherein the insulating film comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and tantalum oxide.

22. The semiconductor device according to claim 19 wherein each of the first and second transistors comprises a source electrode and a drain electrode formed over the oxide semiconductor layer.

23. The semiconductor device according to claim 19, wherein the oxide semiconductor layer is amorphous.

24. The semiconductor device according to claim 19, wherein the oxide semiconductor layer contains an insulating impurity.

25. The semiconductor device according to claim 19 wherein each of the first transistor and the second transistor is an enhancement transistor.

26. A semiconductor device comprising a circuit, the circuit comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,

wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,

wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,

wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,

wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,

wherein each of the first, second, third and fourth transistors comprises an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer comprising an In—

Sn—

Zn—

O based semiconductor.

27. The semiconductor device according to claim 26,

wherein a gate of the first transistor is electrically connectable to a third terminal of the driver IC,

wherein a gate of the second transistor is electrically connectable to a fourth terminal of the driver IC,

wherein a gate of the third transistor is electrically connectable to the third terminal of the driver IC, and

wherein a gate of the fourth transistor is electrically connectable to the fourth terminal of the driver IC.

28. The semiconductor device according to claim 26 wherein each of the first, second, third and fourth transistors is a bottom-gate n-channel transistor.

29. The semiconductor device according to claim 26 further comprising an insulating film over the oxide semiconductor layer, wherein the insulating film comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and tantalum oxide.

30. The semiconductor device according to claim 26 wherein each of the first, second, third and fourth transistors comprises a source electrode and a drain electrode formed over the oxide semiconductor layer.

31. The semiconductor device according to claim 26, wherein the oxide semiconductor layer is amorphous.

32. The semiconductor device according to claim 26, wherein the oxide semiconductor layer contains an insulating impurity.