SEMICONDUCTOR DEVICE

• US 20110210391A1
• Filed: 02/24/2011
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KITAGAWA, Mitsuhiko
• Granted Patent: US 9,024,382 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, the semiconductor device includes a drift region including a semiconductor of a first conductivity type; a first semiconductor region of a second conductivity type provided adjacently to the drift region; a main electrode, a plurality of first gate electrodes and a second gate electrode. The main electrode is provided adjacently to the first semiconductor region and electrically connected to the first semiconductor region, the first semiconductor region being disposed between the drift region and the main electrode. The first gate electrodes are provided along a boundary between the drift region and the first semiconductor region. The first gate electrode has a trench structure and faces the drift region and the first semiconductor region via a first gate insulating film. The second gate electrode of the trench structure is provided along the boundary between the drift region and the first semiconductor region. The second gate electrode is disposed between the two first gate electrodes and faces the drift region and the first semiconductor region via a second gate insulating film. A first portion facing the first semiconductor region in the second gate electrode is shorter than a second portion facing the first semiconductor region in the first gate electrode in a direction from the boundary to the main electrode. The main electrode is extended to a position close to the second gate electrode in the trench provided in the direction from the main electrode to the second gate electrode between the two first gate electrodes. The main electrode is in contact with the first semiconductor region exposed to an inner wall surface of the trench between an end of the first gate electrode on the main electrode side and an end of the second gate electrode on the main electrode side.

Claims

1. A semiconductor device comprising:

a drift region including a semiconductor of a first conductivity type;

a first semiconductor region of a second conductivity type provided adjacently to the drift region;

a main electrode provided adjacently to the first semiconductor region and electrically connected to the first semiconductor region, the first semiconductor region being disposed between the drift region and the main electrode;

a plurality of first gate electrodes provided along a boundary between the drift region and the first semiconductor region, the first gate electrode having a trench structure and facing the drift region and the first semiconductor region via a first gate insulating film; and

a second gate electrode of the trench structure provided along the boundary between the drift region and the first semiconductor region, the second gate electrode being disposed between the two first gate electrodes and facing the drift region and the first semiconductor region via a second gate insulating film, a first portion facing the first semiconductor region in the second gate electrode being shorter than a second portion facing the first semiconductor region in the first gate electrode in a direction from the boundary to the main electrode; and

the main electrode being extended to a position close to the second gate electrode in the trench provided in the direction from the main electrode to the second gate electrode between the two first gate electrodes; and

the main electrode being in contact with the first semiconductor region exposed to an inner wall surface of the trench between an end of the first gate electrode on the main electrode side and an end of the second gate electrode on the main electrode side.

2. The device according to claim 1, further comprising

a second semiconductor region of the first conductivity type between the first semiconductor region and the main electrode, wherein

the main electrode is in contact with the first semiconductor region exposed to the inner wall surface of the trench between the second semiconductor region and the drift region.

3. The device according to claim 2, wherein

a width of the main electrode in contact with the first semiconductor region is 0.05 μ

m or more in a direction from the second semiconductor region to the drift region on the inner wall surface of the trench between the second semiconductor region and the drift region.

4. The device according to claim 1, wherein

a distance between the second gate electrode and an end of the main electrode extended and opposed to the second gate electrode is 0.05 μ

m or more on the inner wall surface side of the trench.

5. The device according to claim 2, further comprising

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode, wherein

the second semiconductor region and the sixth semiconductor region are alternately provided in contact with the first semiconductor region.

6. The device according to claim 2, further comprising

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode, wherein

the second semiconductor region is in contact with the first semiconductor region and extended along the first gate electrode, and the sixth semiconductor region is in contact with the first semiconductor region and extended along the second gate electrode.

7. The device according to claim 2, further comprising a third semiconductor region provided in the surface of the first semiconductor region exposed in an inner wall surface of the trench between the second semiconductor region and the drift region, wherein

the main electrode is extended on and in contact with the third semiconductor region doped with an impurity of the second conductivity type at higher concentration than the first semiconductor region.

8. The device according to claim 1, wherein

the drift region includes a fourth semiconductor region of a first conductivity type and a fifth semiconductor region of a second conductivity type alternately provided in a direction along the boundary between the drift region and the first semiconductor region.

9. The device according to claim 2, further comprising

a seventh semiconductor region of the second conductivity type provided adjacently to the drift region, the drift region being disposed between the first semiconductor region and the seventh semiconductor region.

10. The device according to claim 1, further comprising

an insulating layer in contact with the drift region and the first semiconductor region, wherein

the drift region and the first semiconductor region are provided adjacently on the main surface of the insulating layer;

and

the first gate electrode and the second gate are extended into the trench communicating with the insulating layer from the surfaces of the drift region and the first semiconductor region, respectively.

11. The device according to claim 10, further comprising

a second semiconductor region of the first conductivity type provided adjacently to the first semiconductor region, the first semiconductor region being disposed between the drift region and the second semiconductor region, wherein

the main electrode is provided in contact with a side face of the second semiconductor region, sandwiching the second semiconductor region with the first semiconductor region.

12. The device according to claim 10, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type alternately provided in a direction parallel with the main surface of the insulating layer along the boundary between the drift region and the first semiconductor region.

13. The device according to claim 10, wherein

the drift region includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type alternately laminated on the insulating layer.

14. The device according to claim 11, further comprising

a sixth semiconductor region of the second conductivity type between the first semiconductor region and the main electrode, wherein

the second semiconductor region and the sixth semiconductor region are alternately provided on the insulating layer.

15. The device according to claim 10, wherein

the insulating film is one of a semi-insulating layer and a SiO₂ film provided on a substrate.

16. The device according to claim 2, wherein

the drift region is provided on a first main surface of a semiconductor layer of the first conductivity type;

the first semiconductor region is provided in the drift region;

the second semiconductor region is provided in the first semiconductor region;

the main electrode is provided in contact with the second semiconductor region in the trench provided communicating with the first semiconductor region from the surface of the second semiconductor region; and

the first gate electrode and the second gate electrode are provided in the trench formed in a direction toward a second main surface of the semiconductor layer along the boundary between the drift region and the first semiconductor region.

17. The device according to claim 16, wherein

the first gate electrode and the second gate electrode are provided from the surface of the first semiconductor region to a depth where the first semiconductor region is penetrated.

18. The device according to claim 16, wherein

the first gate electrode and the second gate electrode are provided from the surface across the first semiconductor region, the drift region, and the semiconductor layer to a depth where the first semiconductor region and the drift region are penetrated.

19. The device according to claim 10, wherein

the drift region includes the fourth semiconductor region of the first conductivity type and the fifth semiconductor region of the second conductivity type alternately laminated on the insulating layer;

and

the first semiconductor region includes an eighth semiconductor region of the first conductivity type and a ninth semiconductor region of the second conductivity type alternately laminated on the insulating layer.

20. The device according to claim 19, wherein

a width of the eighth semiconductor region in the lamination direction is smaller than the width of the ninth semiconductor region in the lamination direction.