STRUCTURES OF AND METHODS OF FABRICATING SPLIT GATE MIS DEVICES

• US 20110210406A1
• Filed: 08/26/2010
• Published: 09/01/2011
• Est. Priority Date: 10/20/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Park, Chanho, Gao, Yang, Terrill, Kyle
• Granted Patent: US 9,425,305 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.

Claims

1. A split gate field effect transistor device, comprising:

a split gate structure having a trench, a gate electrode and a source electrode;

first poly layer a disposed within the trench connected to the source electrode;

a second poly layer connected to the gate electrode, wherein the first poly layer and the second poly layer are independent.

2. The device of claim 1, further comprising:

a gate contact connecting the second poly layer; and

a source contact connecting the first poly layer.

3. The device of claim 2, further comprising:

an active region body; and

a source contact, wherein the active region body and the source contact are disposed outside of said trench.

4. The device of claim 3, wherein the same surface plane is established via a CMP compatible process.

5. The device of claim 3, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.

6. A CMP compatible split gate field effect transistor device, comprising:

a split gate structure having a trench, a gate electrode and a source electrode;

first poly layer a disposed within the trench connected to the source electrode;

a second poly layer disposed within the trench connected to the gate electrode, wherein the first poly layer and the second poly layer are independent; and

a metal layer disposed over the split gate structure.

7. The device of claim 6, further comprising:

a gate contact connecting the second poly layer to the gate electrode; and

a source contact connecting the first poly layer to the source electrode.

8. The device of claim 7, further comprising:

an active region body; and

a source contact, wherein the active region body and the source contact are disposed outside of said trench.

9. The device of claim 8, wherein the same surface plane is established via a CMP compatible process.

10. The device of claim 9, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.

11. A planar split gate field effect transistor device, comprising:

a split gate structure having a trench, a gate electrode and a source electrode;

a first poly layer a disposed within the trench and connected to the source electrode;

a second poly layer is disposed within the trench and connected to the gate electrode, wherein the first poly layer and the second poly layer are independent, and wherein the first poly layer and the second poly layer are both disposed within the trench substantially in their entirety.

12. The device of claim 11, further comprising:

a gate contact connecting the second poly layer to the gate electrode; and

a source contact connecting the first poly layer to the source electrode.

13. The device of claim 12, further comprising:

an active region body; and

a source contact, wherein the active region body and the source contact are disposed at a same surface plane.

14. The device of claim 13, wherein the same surface plane is established via a CMP compatible process.

15. The device of claim 14, wherein layout method is used to enable a CMP compatible process to connect the first poly layer to the source electrode and the second poly layer to the gate electrode within said trench.