CHIP PACKAGE
3 Assignments
0 Petitions
Accused Products
Abstract
A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers.
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Citations
56 Claims
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1-20. -20. (canceled)
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21. A circuit component comprising:
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a chip comprising a silicon substrate, a first metal layer over said silicon substrate, a dielectric layer over said first metal layer, a second metal layer over said dielectric layer, said first metal layer and said silicon substrate, an insulating layer on said second metal layer and over said dielectric layer, wherein said second metal layer has multiple contact points not covered by said insulating layer, multiple metal bumps on said multiple contact points, wherein said multiple metal bumps are provided by a copper layer having a thickness between 5 and 50 micrometers; and a first circuit substrate connected to said chip through said metal bumps, wherein said first circuit substrate comprises first, second and third metal traces extending across an edge of said chip, wherein said first, second and third metal traces are provided by a bottommost fan-out metal layer of said first circuit substrate, a first vertical interconnect on said first metal trace and not vertically over said chip, a second vertical interconnect on said second metal trace and not vertically over said chip, and a third vertical interconnect on said third metal trace and not vertically over said chip, wherein said first, second and third vertical interconnects are aligned in a line substantially parallel with said edge and connected to said first, second and third metal traces, respectively, wherein said first, second and third vertical interconnects are sequentially arranged in a same order as the arrangement of said first, second and third metal traces, wherein between said line and said edge from a top perspective view, said first circuit substrate has no metal trace between said first and second metal traces and between said second and third metal traces, wherein from said top perspective view, said first circuit substrate has no vertical interconnect on any metal trace, between said line and said edge, of said bottommost fan-out metal layer of said first circuit substrate, wherein a first pitch between said first and second metal traces at said edge is less than a second pitch between said first and second vertical interconnects, and wherein a third pitch between said second and third metal traces at said edge is less than a fourth pitch between said second and third vertical interconnects. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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30. A circuit component comprising:
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a chip comprising a silicon substrate, a first metal layer over said silicon substrate, a dielectric layer over said first metal layer, a second metal layer over said dielectric layer, said first metal layer and said silicon substrate, an insulating layer on said second metal layer and over said dielectric layer, wherein said second metal layer has multiple contact points not covered by said insulating layer, multiple metal bumps on said multiple contact points, wherein said multiple metal bumps are provided by a copper layer having a thickness between 0.5 and 45 micrometers; and a first circuit substrate connected to said chip through said metal bumps, wherein said first circuit substrate comprises first, second and third metal traces extending across an edge of said chip, wherein said first, second and third metal traces are provided by a bottommost fan-out metal layer of said first circuit substrate, a first vertical interconnect on said first metal trace and not vertically over said chip, a second vertical interconnect on said second metal trace and not vertically over said chip, and a third vertical interconnect on said third metal trace and not vertically over said chip, wherein said first, second and third vertical interconnects are aligned in a line substantially parallel with said edge and connected to said first, second and third metal traces, respectively, wherein said first, second and third vertical interconnects are sequentially arranged in a same order as the arrangement of said first, second and third metal traces, wherein between said line and said edge from a top perspective view, said first circuit substrate has no metal trace between said first and second metal traces and between said second and third metal traces, wherein from said top perspective view, said first circuit substrate has no vertical interconnect on any metal trace, between said line and said edge, of said bottommost fan-out metal layer of said first circuit substrate, wherein a first pitch between said first and second metal traces at said edge is less than a second pitch between said first and second vertical interconnects, and wherein a third pitch between said second and third metal traces at said edge is less than a fourth pitch between said second and third vertical interconnects. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A circuit component comprising:
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a chip comprising a silicon substrate, a first metal layer over said silicon substrate, a dielectric layer over said first metal layer, a second metal layer over said dielectric layer, said first metal layer and said silicon substrate, an insulating layer on said second metal layer and over said dielectric layer, wherein said second metal layer has multiple contact points not covered by said insulating layer, multiple metal bumps on said multiple contact points, wherein said multiple metal bumps are provided by a copper layer having a thickness between 5 and 50 micrometers, wherein a pitch between a first one of said multiple metal bumps and a second one of said multiple metal bumps is less than 35 micrometers; a flexible substrate connected to said chip through said multiple metal bumps; a circuit substrate; and an anisotropic conductive film (ACF) between said flexible substrate and said circuit substrate, wherein said flexible substrate is connected to said circuit substrate through said anisotropic conductive film. - View Dependent Claims (42, 43)
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44. A circuit component comprising:
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a chip comprising a silicon substrate, a first metal layer over said silicon substrate, a dielectric layer over said first metal layer, a second metal layer over said dielectric layer, said first metal layer and said silicon substrate, an insulating layer on said second metal layer and over said dielectric layer, wherein said second metal layer has multiple contact points not covered by said insulating layer, multiple metal bumps on said multiple contact points, wherein said multiple metal bumps are provided by a copper layer having a thickness between 0.5 and 45 micrometers, wherein a pitch between a first one of said multiple metal bumps and a second one of said multiple metal bumps is less than 35 micrometers; a flexible substrate connected to said chip through said multiple metal bumps; a circuit substrate; and an anisotropic conductive film (ACF) between said flexible substrate and said circuit substrate, wherein said flexible substrate is connected to said circuit substrate through said anisotropic conductive film. - View Dependent Claims (45, 46, 47, 48)
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49. A chip comprising:
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a silicon substrate; a first metal layer over said silicon substrate; a dielectric layer over said first metal layer; a second metal layer over said dielectric layer, said first metal layer and said silicon substrate; an insulating layer on said second metal layer and over said dielectric layer, wherein said second metal layer comprises a first portion having a first left region, a first right region and a first contact point between said first left and right regions, wherein said first left and right regions and said first contact point are not covered by said insulating layer, wherein said second metal layer comprises a second portion having a second left region, a second right region and a second contact point between said second left and right regions, wherein said second left and right regions and said second contact point are not covered by said insulating layer; a first metal bump on said first contact point, wherein said first metal bump has a first left sidewall horizontally spaced apart from a left portion of said insulating layer, and said first left region is between said first left sidewall and said left portion, wherein said first metal bump has a first right sidewall horizontally spaced apart from a middle portion of said insulating layer, and said first right region is between said first right sidewall and said middle portion, wherein said insulating layer has no portion between said first left sidewall and said left portion and between said first right sidewall and said middle portion; and a second metal bump on said second contact point, wherein said second metal bump has a second left sidewall horizontally spaced apart from said middle portion, and said second left region is between said second left sidewall and said middle portion, wherein said second metal bump has a second right sidewall horizontally spaced apart from a right portion of said insulating layer, and said second right region is between said second right sidewall and said right portion, wherein said insulating layer has no portion between said second left sidewall and said middle portion and between said second right sidewall and said right portion, wherein said first and second metal bumps are provided by a copper layer having a thickness between 5 and 50 micrometers, wherein a pitch between said first and second metal bumps is less than 35 micrometers. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56)
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Specification