Method of Actively Tagging Electronic Designs and Intellectual Property Cores

• US 20110210829A1
• Filed: 05/10/2011
• Published: 09/01/2011
• Est. Priority Date: 09/08/2006
• Status: Abandoned Application

• Current Assignee: Algotronix Ltd.
• Original Assignee: Algotronix Ltd.
• Inventors: Kean, Thomas A.
• Application Number:
  US13/104,442
• Publication Number:
  US 20110210829A1
• Time in Patent Office: Days
• US Class Current: 340/10.42
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H04K 1/02 by adding a second signal to make the desired signal unintelligible

Abstract

In an embodiment of the invention, an active security tag is embedded within the digital logic of an electronic design for logic destined for an integrated circuit such as an FPGA. The security tag includes security tag data which permits identification of the electronic design, and facilitates efforts to enforce copyrights in the designs. The security tag also includes a transmitter designed to covertly transmit security tag data to a receiver. Other information, such as error information and status information about the integrated circuit may also be transmitted. The transmitted information is concealed from detection by being hidden within background noise signals or other signals created by normal usage of the integrated circuit.

Claims

1. A method for detecting falsely labeled integrated circuits, comprising:

reading tag data from a security tag, the security tag comprising;

tag data which uniquely identifies the electronic design;

a communications channel for interfacing with an external detector, to deliver the tag data to the external detector; and

a transmitter for transmitting the tag data using a tag data signal via the communications channel to the external detector; and

comparing the tag data with a product marking associated with the integrated circuit.

2. A method for enforcing electronic design tool licenses, comprising:

causing an electronic design tool to covertly insert a security tag into a user design, wherein the security tag comprises a digital logic circuit including a transmitter implemented in the user design, and wherein the user design is implemented in an integrated circuit; and

determining whether the security tag is present within the integrated circuit, using an external detection circuit to read tag data transmitted from the security tag by the transmitter.

3. A method for determining design version information on a user design programmed into an FPGA integrated circuit, comprising:

receiving the FPGA integrated circuit, wherein the FPGA integrated circuit comprises a security tag, the security tag comprising information identifying a design and a transmitter for transmitting the information identifying the design, wherein the transmitter comprises a digital logic circuit implemented in the FPGA integrated circuit;

causing the transmitter to transmit the information identifying the design; and

determining the design version by reading the information transmitted by the transmitter, using an external detector.

4. A method for reading information from an integrated circuit, the integrated circuit comprising a security tag and a data link connected to the integrated circuit and to the security tag, the data link for providing the information from the integrated circuit to the security tag, the security tag comprising a communications channel for interfacing with an external detector, to deliver the information to the external detector, and a transmitter for transmitting the information using an information signal via the communications channel to the external detector, comprising:

causing the integrated circuit to begin operating;

causing the integrated circuit to deliver the information to the security tag over the data link;

causing the transmitter to transmit the information over the communications channel to the external detector; and

reading the information using the external detector.

5. The method of claim 4, wherein the information comprises error or status information about the operation of the integrated circuit.

6. The method of claim 4, wherein the transmitter comprises a digital logic circuit implemented in the integrated circuit.