HIGH DEFINITION PERSONAL COMPUTER (PC) CAM

• US 20110211036A1
• Filed: 02/26/2010
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Symmetrix Video Systems LLC (Jeffrey M. Gross)
• Original Assignee: Bao Tran
• Inventors: Tran, Bao
• Granted Patent: US 8,503,539 B2
• Time in Patent Office: Days
• US Class Current: 348/14.08
• CPC Class Codes: G06F 3/005 Input arrangements through a video camera
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 23/64 Computer-aided capture of images, e.g. transfer from script file into camera, check of taken image quality, advice or proposal for image composition or decision on when to take image
• CPC Class Codes: H04N 23/698 for achieving an enlarged field of view, e.g. panoramic image capture
• CPC Class Codes: H04N 23/80 Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 5/2628 Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
• CPC Class Codes: H04N 5/265 Mixing
• CPC Class Codes: H04N 7/12 Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal H04N7/24 takes precedence
• CPC Class Codes: H04N 7/15 Conference systems
• CPC Class Codes: H04N 7/181 for receiving images from a plurality of remote sources

Abstract

A video system includes a central processing unit (CPU) and a graphic processing unit (GPU) including a plurality of processors therein. The system also includes a high definition (HD) imager; a serial bus controller coupled to the imager, the CPU and the GPU to communicate data between the HD imager and the CPU or the GPU over a serial bus having a transmit differential signal pair, a receive differential pair and a compatibility differential signal pair for interoperability with another serial bus version; and computer code executable by the processors in the GPU to encode in parallel the video transmitted over the serial bus controller and to minimize high definition encoding workload on the CPU.

Claims

1. A video system including a central processing unit (CPU) and a graphic processing unit (GPU) including a plurality of processors therein, comprising

a high definition (HD) imager;

a serial bus controller coupled to the imager, the CPU and the GPU to communicate data between the HD imager and the CPU or the GPU over a serial bus having a transmit differential signal pair, a receive differential pair and a compatibility differential signal pair for interoperability with another serial bus version; and

computer code executable by the processors in the GPU to encode in parallel the video transmitted over the serial bus controller and to minimize high definition encoding workload on the CPU.

2. The system of claim 1, wherein the serial bus comprises Super Speed Universal Serial Bus.

3. The system of claim 1, wherein the GPU performs Scalable Video Coding (SVC) or advanced video coding (AVC).

4. The system of claim 1, wherein the GPU performs gesture recognition.

5. The system of claim 1, wherein the GPU performs video analytics and or H.264 encoding.

6. The system of claim 1, comprising computer code executable by the CPU for high definition video conferencing or Skype video conferencing.

7. The system of claim 1, comprising a cloud based data storage to receive encoded video from the GPU or an elastic compute cloud to process the encoded video from the GPU.

8. The system of claim 1, wherein the GPU stitches videos in real time from a plurality of cameras to provide at least a 180 degree view.

9. The system of claim 1, comprising computer code executable by the CPU to conform to user preference on resolution, quality of encode, speed of encode, CPU utilization, or power.

10. The system of claim 9, comprising computer code to:

a. if CPU utilization is below a predetermined threshold set by the CPU utilization preference, encode at highest quality or speed;

b. if CPU utilization is above the predetermined threshold, progressively decrease quality or speed of encoding until user preference settings are met; and

c. if CPU utilization is still above the predetermined threshold after decreasing quality or encoding speed, progressively decrease resolution until CPU utilization is below the predetermined threshold.

17. The system of claim 1, comprising computer code executable by the CPU to conform to user preference on resolution, quality of encode, speed of encode, CPU utilization, or power.

18. The system of claim 9, comprising computer code to:

a. if CPU utilization is below a predetermined threshold set by the CPU utilization preference, encode at highest quality or speed;

b. if CPU utilization is above the predetermined threshold, progressively decrease quality or speed of encoding until user preference settings are met; and

c. if CPU utilization is still above the predetermined threshold after decreasing quality or encoding speed, progressively decrease resolution until CPU utilization is below the predetermined threshold.

19. The system of claim 1, wherein the serial bus comprises Super Speed Universal Serial Bus.

20. The system of claim 1, comprising a cloud based data storage to receive encoded video from the GPU or an elastic compute cloud to process the encoded video from the GPU.

11. A video system including a central processing unit (CPU) and a graphic processing unit (GPU) including a plurality of processors therein, comprising:

a high definition (HD) imager;

an ultra-wideband (UWB) wireless transceiver coupling the imager, the CPU and the GPU; and

computer code executable by the processors in the GPU to encode the video communicated using UWB.

12. The system of claim 11, wherein the GPU performs advanced video coding (AVC).

13. The system of claim 11, wherein the GPU performs video analytics and advanced video coding (AVC).

14. The system of claim 11, comprising computer code to conform to user preference on resolution, quality of encode, speed of encode, CPU utilization, or power.

15. The system of claim 14, comprising computer code to:

a. if CPU utilization is below a predetermined threshold set by the CPU utilization preference, encode at highest quality or speed;

b. if CPU utilization is above the predetermined threshold, progressively decrease quality or speed of GPU encoding until user preference settings are met; and

c. if CPU utilization is still above the predetermined threshold after decreasing quality or encoding speed, progressively decrease resolution until CPU utilization is below the predetermined threshold.

16. A video system including a central processing unit (CPU) and a graphic processing unit (GPU) including a plurality of processors therein, comprising

a high definition (HD) imager;

a serial bus controller coupled to the imager, the CPU and the GPU to communicate data between the HD imager and the CPU or the GPU over a serial bus having a transmit differential signal pair, a receive differential pair and a compatibility differential signal pair for interoperability with a prior serial bus version;

computer code executable by the processors in the GPU to encode the video transmitted over the serial bus controller;

computer code executable by the GPU to stitch videos in real time from a plurality of cameras to provide at least a 180 degree view; and

computer code executable by the CPU for high definition video conferencing or Skype video conferencing.