INTEGRATED CIRCUIT HAVING VARIABLE MEMORY ARRAY POWER SUPPLY VOLTAGE
First Claim
1. An integrated circuit comprising:
- a memory array comprising;
a plurality of memory cells arranged in a grid of rows and columns;
a first conductor coupled to a power supply voltage terminal of each of the plurality of memory cells;
a second conductor coupled to receive a power supply voltage; and
a plurality of dummy cells, wherein a transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode; and
a bias circuit coupled to the control electrode of the transistor.
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Accused Products
Abstract
An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor is coupled to receive a power supply voltage. The memory array also includes a plurality of dummy cells. A transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode. The bias circuit is coupled to the control electrode of the transistor.
89 Citations
20 Claims
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1. An integrated circuit comprising:
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a memory array comprising; a plurality of memory cells arranged in a grid of rows and columns; a first conductor coupled to a power supply voltage terminal of each of the plurality of memory cells; a second conductor coupled to receive a power supply voltage; and a plurality of dummy cells, wherein a transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode; and a bias circuit coupled to the control electrode of the transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a memory array comprising; a plurality of memory cells arranged in a grid of rows and columns; a first conductor coupled to a power supply voltage terminal of each of the plurality of memory cells; a second conductor coupled to receive a power supply voltage; and a plurality of dummy cells, wherein a transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode; a bias circuit coupled to the control electrode of the transistor; and a mode select transistor having a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode coupled to receive a mode signal, wherein the mode select transistor couples the first conductor to the second conductor in response to the mode signal being asserted. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit comprising:
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a memory array comprising; a plurality of memory cells arranged in a grid of rows and columns; a first conductor coupled to a power supply voltage terminal of each of the plurality of memory cells; a second conductor coupled to ground; and a plurality of dummy cells on an edge of the grid of rows and columns, wherein a transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode; a bias circuit coupled to the control electrode of the transistor; - View Dependent Claims (17, 18, 19, 20)
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Specification