SEMICONDUCTOR MEMORY MODULE

• US 20110211414A1
• Filed: 02/08/2011
• Published: 09/01/2011
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: MUSHA, Tatsunori
• Granted Patent: US 8,400,869 B2
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.

Claims

1. A semiconductor device comprising:

a plurality of semiconductor memories;

a clock signal synchronization circuit electrically coupled to the plurality of semiconductor memories; and

a first circuit electrically coupled to the plurality of semiconductor memories, the first circuit changing a bit width of data, the data being transferred between the first circuit and the plurality of semiconductor memories.

2. The semiconductor device according to claim 1, wherein the clock signal synchronization circuit is electrically coupled to the first circuit,

wherein the clock signal synchronization circuit generates a first clock synchronized with an external clock, and

wherein the first circuit receives the first clock.

3. The semiconductor device according to claim 1, further comprising:

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock.

4. The semiconductor device according to claim 3, wherein the first circuit receives the second clock from the dividing circuit,

wherein the first circuit receives the first clock from the clock signal synchronization circuit, and

wherein the first circuit operates based on the first and second clocks.

5. The semiconductor device according to claim 4, wherein the first circuit increases the bit width of the data when the semiconductor device is placed in write operation.

6. The semiconductor device according to claim 4, wherein the first circuit decreases the bit width of the data when the semiconductor device is placed in read operation.

7. The semiconductor device according to claim 3, wherein the dividing circuit supplies the second clock to the plurality of semiconductor memories.

8. The semiconductor device according to claim 1, wherein the first circuit comprises a parallel-serial conversion circuit.

9. The semiconductor device according to claim 1, wherein the clock signal synchronization circuit and the first circuit are integrated on an interface chip.

10. The semiconductor device according to claim 1, wherein the plurality of semiconductor memories perform a first burst operation with a first burst length, the first circuit performs a second burst operation with a second burst length, the first burst length is shorter than the second burst length.

11. The semiconductor device according to claim 1, wherein the plurality of semiconductor memories is configured to form a plurality of banks

12. The semiconductor device according to claim 1, further comprising:

a boosted voltage generation circuit supplying a boosted voltage to the plurality of the semiconductor memories.

13. The semiconductor device according to claim 11, further comprising:

a plurality of command decoders, each of the plurality of command decoders corresponding to a corresponding one of the plurality of banks

14. The semiconductor device according to claim 13, wherein each of the plurality of command decoders decodes a command to the corresponding one of the plurality of banks, the corresponding one is placed in an active mode or a standby mode according to the command.

15. The semiconductor device according to claim 1, further comprising:

an error correcting code circuit adding error correction code bit data to data to be written in the plurality of the semiconductor memories.

16. The semiconductor device according to claim 1, wherein the clock signal synchronization circuit is electrically coupled in parallel to the plurality of semiconductor memories, wherein the first circuit is electrically coupled in parallel to the plurality of semiconductor memories.

17. The semiconductor device according to claim 1, further comprising:

a bus width switch switching a bit number of data to be input into the first circuit.

18. A semiconductor device comprising:

a plurality of semiconductor memories; and

an interface chip electrically coupled in parallel to the plurality of semiconductor memories,

wherein the interface chip comprises;

a clock signal synchronization circuit generating a first clock synchronized with an external clock;

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock, the dividing circuit supplying the second clock to the plurality of semiconductor memories; and

a parallel-serial conversion circuit electrically coupled to the plurality of semiconductor memories, the parallel-serial conversion circuit increasing a first bit width of data to be transferred to the plurality of semiconductor memories when the semiconductor device is placed in write operation, the parallel-serial conversion circuit decreasing a second bit width of data to have been transferred from the plurality of semiconductor memories when the semiconductor device is placed in read operation.

19. The semiconductor device according to claim 18, wherein the interface chip further comprises:

a command decoder decoding a command to at least one of the plurality of semiconductor memories, the at least one of the plurality of semiconductor memories performing an operation according to the command.

20. A semiconductor device comprising:

a plurality of banks, each of the plurality of banks comprising a plurality of semiconductor memories;

an interface chip electrically coupled in parallel to the plurality of semiconductor memories; and

a boosted voltage generation circuit supplying a boosted voltage to the plurality of the semiconductor memories,

wherein the interface chip comprises;

a clock signal synchronization circuit generating a first clock synchronized with an external clock;

a dividing circuit receiving the first clock from the clock signal synchronization circuit, the dividing circuit generating a second clock from the first clock, the second clock being in synchronism with the first clock, and the second clock having a different frequency from that of the first clock, the dividing circuit supplying the second clock to the plurality of semiconductor memories;

a plurality of command decoders, each of the plurality of command decoders corresponding to a corresponding one of the plurality of banks;

a parallel-serial conversion circuit electrically coupled to the plurality of semiconductor memories, the parallel-serial conversion circuit increasing a first bit width of data to be transferred to the plurality of semiconductor memories when the semiconductor device is placed in write operation, the parallel-serial conversion circuit decreasing a second bit width of data to have been transferred from the plurality of semiconductor memories when the semiconductor device is placed in read operation;

an error correcting code circuit adding error correction code bit data to data to be written in the plurality of the semiconductor memories; and

a bus width switch switching a bit number of data to be input into the parallel-serial conversion circuit.