SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110212571A1
• Filed: 05/10/2011
• Published: 09/01/2011
• Est. Priority Date: 12/26/2008
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun, SAKATA, Junichiro
• Application Number:
  US13/104,551
• Publication Number:
  US 20110212571A1
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by sputtering in a sputtering chamber using a target comprising an In—

Sn—

Zn—

O based semiconductor; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.

7. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, further comprising a step of forming a gate electrode over the substrate prior to the formation of the first oxide semiconductor layer.

8. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein a bias voltage is applied to the substrate during the formation of the first oxide semiconductor layer.

9. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein at least one of the first and second oxide semiconductor layers is amorphous.

10. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein the target includes an insulating impurity.

11. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, further comprising a step of forming an insulating layer comprising aluminum oxide over the second oxide semiconductor layer.

12. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein the first oxide semiconductor layer is formed in an oxygen atmosphere.

13. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein the etching is dry etching.

14. The method of manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 and 6, wherein the etching is wet etching.

2. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by sputtering in a sputtering chamber using a target comprising indium oxide, tin oxide and zinc oxide; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.

3. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by DC sputtering in a sputtering chamber using a target comprising an In—

Sn—

Zn—

O based semiconductor; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.

4. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by DC sputtering in a sputtering chamber using a target comprising indium oxide, tin oxide and zinc oxide; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.

5. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by pulsed DC sputtering in a sputtering chamber using a target comprising an In—

Sn—

Zn—

O based semiconductor; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.

6. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer over a substrate by pulsed DC sputtering in a sputtering chamber using a target comprising indium oxide, tin oxide and zinc oxide; and

removing a portion of the first oxide semiconductor layer by etching to form a second oxide semiconductor layer including a channel formation region.