THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME

• US 20110212580A1
• Filed: 05/06/2011
• Published: 09/01/2011
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Mo, Steve Y. G., Park, Jin-Seong, Jeong, Jae-Kyeong, Kim, Kwang-Suk, Jeong, Jong-Han
• Granted Patent: US 8,247,266 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT) using an oxide semiconductor layer as an active layer, a method of manufacturing the TFT, and a flat panel display (FPD) including the TFT are taught. The TFT includes a gate electrode formed on a substrate, an oxide semiconductor layer electrically insulated from the gate electrode by a gate insulating layer, and the oxide semiconductor layer including a channel region, a source region, and a drain region, and a source electrode and a drain electrode respectively electrically contacting the source region and the drain region. The oxide semiconductor layer is formed of an InZnO or IZO layer (indium zinc oxide layer) including Zr. The carrier density of the IZO layer is controlled to be 1×10¹³ to 1×10¹⁸ #cm⁻³ by controlling an amount of Zr.

Claims

1-2. -2. (canceled)

3. A method of manufacturing a TFT, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer covering the gate electrode on the substrate;

forming an oxide semiconductor layer that provides a channel region, a source region, and a drain region on the gate insulating layer; and

forming a source electrode and a drain electrode that respectively contact the source region and the drain region

wherein the step of forming an oxide semiconductor layer further comprising the steps of depositing ions including In, Zn, and Zr from a target to form an IZO (indium zinc oxide) layer comprising Zr on the gate insulating layer, and

controlling a carrier density of the IZO layer by controlling an amount of Zr.

4. The method as claimed in claim 3, in which the target comprises an InZnO target and a Zr target.

5. The method as claimed in claim 4, in which a magnitude of bias power applied to the Zr target is controlled to control an amount of Zr.

6. The method as claimed in claim 4, in which an intensity of pulse laser radiated on the Zr target is controlled to control an amount of Zr.

7. The method as claimed in claim 3, in which an amount of Zr is controlled so that a carrier density of the IZO layer is 1×

10¹³ to 1×

10¹⁸ #cm<sup>−

3</sup> by controlling the amount of Zr, where # refers to number of carriers.

8. The method as claimed in claim 3, in which an amount of Zr is controlled in a range of from 20 At % to 0 At % arranged in a decreasing order.

9-12. -12. (canceled)