Method for Forming Shielded Gate Field Effect Transistors

• US 20110212586A1
• Filed: 04/06/2011
• Published: 09/01/2011
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Ashok Challa, Christopher Boguslaw Kocon, Gary M. Dolny, Joseph A. Yedinak, Nathan Lawrence Kraft, Rodney Ridley, Thomas E. Grebs
• Inventors: Dolny, Gary M., Challa, Ashok, Kocon, Christopher Boguslaw, Yedinak, Joseph A., Kraft, Nathan Lawrence, Grebs, Thomas E., Ridley, Rodney
• Granted Patent: US 8,803,207 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED.

Claims

1-21. -21. (canceled)

22. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining lower sidewalls and bottom surface of the trench;

after forming the dielectric layer, filling a lower portion of the trench with a shield electrode;

forming an inter-electrode dielectric (IED) in the trench over the shield electrode, comprising;

carrying out a steam ambient oxidation;

carrying out a dry ambient oxidation; and

forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

23. The method of claim 22 wherein the dry ambient oxidation is carried out at a higher temperature than a temperature at which the steam ambient oxidation is carried out.

24. The method of claim 22 wherein the step of forming an IED further comprises carrying out an inert anneal in an inert ambient.

25. The method of claim 24 wherein the inert ambient is one of nitrogen and argon.

26. The method of claim 22 wherein the semiconductor region has a first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region flanking the trench.

27. The method of claim 22 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend through the epitaxial layer and terminate within the substrate.

28. The method of claim 22 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend into and terminate within the epitaxial layer.

29. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining lower sidewalls and bottom surface of the trench;

after forming the dielectric layer, filling a lower portion of the trench with a shield electrode;

forming an inter-electrode dielectric (IED) in the trench over the shield electrode, comprising;

carrying out a steam ambient oxidation;

carrying out an inert anneal in an inert ambient; and

forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

30. The method of claim 29 wherein the inert ambient is one of nitrogen and argon.

31. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining lower sidewalls and bottom surface of the trench;

after forming the dielectric layer, filling a lower portion of the trench with a shield electrode;

forming an inter-electrode dielectric (IED) in the trench over the shield electrode, comprising;

forming an oxide layer using one high density plasma process and sub-atmospheric chemical vapor deposition;

carrying out a dry ambient oxidation; and

forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

32. The method of claim 31 wherein the step of forming an IED further comprises carrying out an inert anneal in an inert ambient.

33. The method of claim 32 wherein the inert ambient is one of nitrogen and argon.

34. The method of claim 31 wherein the step of forming an IED further comprises carrying out a steam ambient oxidation.

35. The method of claim 34 wherein the dry ambient oxidation is carried out at a higher temperature than a temperature at which the steam ambient oxidation is carried out.

36-71. -71. (canceled)