FLASH-based Memory System with Static or Variable Length Page Stripes Including Data Protection Information and Auxiliary Protection Stripes

• US 20110213920A1
• Filed: 05/09/2011
• Published: 09/01/2011
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Frost, Holloway H., Camp, Charles J.
• Granted Patent: US 8,560,881 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area

Abstract

Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Claims

1. A controller for use in a solid state storage system including a plurality of FLASH memory devices, the controller comprising:

(a) a buffer adapted to store information reflecting blocks of memory within the FLASH memory devices that were previously used to store data and that are available for storage of different data;

(b) block stripe assembly circuitry for assembling block stripes using the information contained in the buffer, each block stripe comprising three or more blocks, each block corresponding to a group of memory locations within a given FLASH memory device, each block within a given block stripe being located within a FLASH memory device different from the FLASH memory devices in which the other blocks in the block stripe are located, wherein the block stripe assembly circuitry determines the number of blocks to be included in each assembled block stripe based on the information in the buffer;

(c) data protection circuitry for generating data protection information using a first group of data items;

(d) circuitry for associating each data item in the first group of data items with a memory location in a block of a first block stripe, each data item being associated with a memory location in a different block of the first block stripe from other data items, and for associating the data protection information generated using the first group of data items with a memory location in a block within the first block stripe that is different from the blocks used in storing the first group of data items; and

(e) auxiliary data protection circuitry for generating auxiliary data protection information using data items associated with memory locations in the same block for each block within the first block stripe.

2. The controller of claim 1, wherein the data protection circuitry includes circuitry for performing a bitwise logical operation on each data item in the first group of data items.

3. The controller of claim 1, wherein the controller comprises a field programmable gate array (“

FPGA”

).

4. The controller of claim 1, further comprising circuitry for associating each block with a specific plane identifier and wherein the block stripe assembly circuitry is configured such that blocks within an assembled block stripe are associated with the same plane identifier.

5. The controller of claim 1, further comprising circuitry for generating page stripes, where each page stripe is associated with a plurality of memory locations and each memory location associated with a given page stripe is within the same block stripe.

6. The controller of claim 5, further including circuitry for associating each memory location with a specific page identifier, wherein the circuitry for generating page stripes is configured such that all of the memory locations associated with a given page stripe have the same page identifier.

7. A method of controlling a solid state storage system having a plurality of FLASH memory devices, the method comprising:

(a) buffering information reflecting blocks of memory within the FLASH memory devices that were previously used to store data and that are available for storage of different data;

(b) assembling block stripes using the buffered information, each block stripe comprising three or more blocks, each block corresponding to a group of memory locations within a given FLASH memory device, each block within a given block stripe being located within a FLASH memory device different from the FLASH memory devices in which the other blocks in the block stripe are located;

(c) determining the number of blocks to be included in each assembled block stripe based on the buffered information;

(d) generating data protection information using a first group of data items;

(e) associating each data item in the first group of data items with a memory location in a block of a first block stripe, each data item in the first group of data items being associated with a memory location in a different block of the first block stripe from other data items in the first group of data items;

(f) associating the data protection information generated using the first group of data items with a memory location in a block within the first block stripe that is different from the blocks associated with the first group of data items; and

(g) generating auxiliary data protection information using data items associated with memory locations in the same block for each block within the first block stripe.

8. The method of claim 7, wherein generating the data protection information involves performing a bitwise logical operation on each data item in the first group of data items.

9. The method of claim 7, wherein the method is implemented using at least a field programmable gate array (“

FPGA”

).

10. The method of claim 7, further comprising associating each block with a specific plane identifier such that blocks within an assembled block stripe are associated with the same plane identifier.

11. The method of claim 7, further comprising generating page stripes for the first block stripe, where each page stripe is associated with a plurality of memory locations and each memory location associated with a given page stripe is within the same block stripe.

12. The controller of claim 11, further comprising associating each memory location with a specific page identifier, wherein the page stripes are generated such that all of the memory locations associated with a given page stripe have the same page identifier.

13. The method of claim 7, wherein the first block stripe has a different number of blocks from a second block stripe in the solid state storage system.

14. A solid state storage system, comprising:

a printed circuit board;

a plurality of FLASH memory devices mounted on the printed circuit board;

communication buses connected to the FLASH memory devices; and

a controller connected to the communication buses for controlling the FLASH memory devices, the controller configured to;

(a) buffer information reflecting blocks of memory within the FLASH memory devices that were previously used to store data and that are available for storage of different data;

(b) assemble block stripes using the buffered information, each block stripe comprising three or more blocks, each block corresponding to a group of memory locations within a given FLASH memory device, each block within a given block stripe being located within a FLASH memory device different from the FLASH memory devices in which the other blocks in the block stripe are located;

(c) determine the number of blocks to be included in each assembled block stripe based on the buffered information;

(d) generate data protection information using a first group of data items;

(e) associate each data item in the first group of data items with a memory location in a block of a first block stripe, each data item in the first group of data items being associated with a memory location in a different block of the first block stripe from other data items in the first group of data items;

(f) associate the data protection information generated using the first group of data items with a memory location in a block within the first block stripe that is different from the blocks associated with the first group of data items; and

(g) generate auxiliary data protection information using data items associated with memory locations in the same block for each block within the first block stripe.

15. The system of claim 14, wherein the controller generates data protection information at least by performing a bitwise logical operation on each data item in the first group of data items.

16. The system of claim 14, wherein the controller is implemented using at least a field programmable gate array (“

FPGA”

).

17. The system of claim 14, wherein the controller is configured to associate each block with a specific plane identifier such that blocks within an assembled block stripe are associated with the same plane identifier.

18. The system of claim 14, wherein the controller is configured to generate page stripes, wherein each page stripe is associated with a plurality of memory locations and each memory location associated with a given page stripe is within the same block stripe.

19. The system of claim 18, wherein the controller is configured to associate each memory location with a specific page identifier such that memory locations associated with a given page stripe have the same page identifier.

20. The system of claim 14, wherein the first block stripe has a greater number of blocks than a second block stripe in the solid state storage system.