Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules
First Claim
1. A multi-level flash memory storage system comprising:
- a host which uses a downstream interface to a plurality of multi-level flash memory storage subsystems;
a plurality of multi-level flash memory storage subsystems, each multi-level flash memory storage subsystem further comprising;
volatile memory sector buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected;
a Smart Storage Switch (SSS) which comprises;
an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address;
a smart storage transaction manager that manages transactions from the host;
a virtual storage processor that maps the host address to an assigned flash module to generate a Logical Block Address (LBA), the virtual storage processor performing a first level of mapping;
a virtual storage bridge between the smart storage transaction manager and a LBA bus;
a first-level stripping mapper, in the Smart Storage Switch, that maps the LBA to a plurality of flash memory modules;
wherein first-level striping is performed before the host data is sent to flash memory modules;
a plurality of flash memory modules, wherein a flash module in the plurality of flash modules comprises;
a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and to receive the host data from the virtual storage bridge;
a second-level mapper, in the NVM controller, for mapping the LBA to a Physical Block Address (PBA);
a local clock source, within each of the plurality of flash modules, for generating local clocks for clocking the NVM controllers and interfaces to raw-NAND flash memory chips;
wherein local clocks are generated within each of the plurality of flash modules;
raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller,whereby address mapping is performed to access the raw-NAND flash memory chips.
1 Assignment
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Accused Products
Abstract
A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
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Citations
21 Claims
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1. A multi-level flash memory storage system comprising:
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a host which uses a downstream interface to a plurality of multi-level flash memory storage subsystems; a plurality of multi-level flash memory storage subsystems, each multi-level flash memory storage subsystem further comprising; volatile memory sector buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected; a Smart Storage Switch (SSS) which comprises; an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a Logical Block Address (LBA), the virtual storage processor performing a first level of mapping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a first-level stripping mapper, in the Smart Storage Switch, that maps the LBA to a plurality of flash memory modules; wherein first-level striping is performed before the host data is sent to flash memory modules; a plurality of flash memory modules, wherein a flash module in the plurality of flash modules comprises; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and to receive the host data from the virtual storage bridge; a second-level mapper, in the NVM controller, for mapping the LBA to a Physical Block Address (PBA); a local clock source, within each of the plurality of flash modules, for generating local clocks for clocking the NVM controllers and interfaces to raw-NAND flash memory chips;
wherein local clocks are generated within each of the plurality of flash modules;raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller, whereby address mapping is performed to access the raw-NAND flash memory chips. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A flash memory module comprising:
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module interface means, coupled to a host, for receiving commands to access flash memory and for receiving data and an address; a Non-Volatile Memory (NVM) controller, coupled to a LBA bus to receive a LBA from the module interface means; a local clock source, receiving a clock from the module interface means, for generating local clocks for clocking NVM controllers and interfaces to the flash memory, data striping mapping means for dividing the data into data segments that are assigned to different ones of a plurality of NVM memory devices; a plurality of NVM memory devices comprising; flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block; wherein the flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel; a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a NVM controller and a physical block address (PBA) indicating a location of the data within the flash memory; wherein the mapping entries further comprise a plane number and a page number; a table restorer, coupled to a physical sequential address counter, for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of the flash memory in a plane-interleaved order determined by the physical sequential address counter, wherein the volatile logical-physical mapping table is restored from flash memory in a plane-interleaved order using a second least-significant-bit (LSB) as a most-significant bit (MSB) of the physical block address. - View Dependent Claims (8, 9, 10, 11)
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12. A flash memory storage system comprising:
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a host which uses a downstream interface to a multi-level flash memory storage subsystem; wherein the multi-level flash memory storage subsystem comprises; a smart storage switch (SSS) which comprises; an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a flash memory module which comprises; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the data from the virtual storage bridge; a local clock source, within the flash module, for generating a local clock for clocking the NVM controller and interface to raw-NAND flash memory chips, wherein the local clock is generated within each flash module; raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by a remapping unit in the NVM controller; a remapping unit for converting logical addresses received from the virtual storage bridge into physical addresses for accessing a plurality of NVM memory blocks in the flash memory module; whereby address mapping is performed to access the raw-NAND flash memory chips. - View Dependent Claims (13, 14, 15)
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16. A multi-level flash memory storage system comprising:
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volatile memory sector buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected; a Smart Storage Switch (SSS) which comprises; an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a Logical Block Address (LBA), the virtual storage processor performing a first level of mapping; a virtual storage bridge between the smart storage transaction manager and a LBA bus; and a first-level stripping mapper, in the Smart Storage Switch, that maps the LBA to a plurality of flash memory modules; wherein first-level striping is performed before the host data is sent to flash memory modules. - View Dependent Claims (17, 18)
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19. A flash memory storage system comprising:
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a smart storage switch (SSS) which comprises; an upstream interface to a host for receiving host commands to access Non-Volatile Memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping; and a virtual storage bridge between the smart storage transaction manager and a LBA bus. - View Dependent Claims (20, 21)
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Specification