METHOD OF WAKING PROCESSOR FROM SLEEP MODE

• US 20110213992A1
• Filed: 02/28/2010
• Published: 09/01/2011
• Est. Priority Date: 02/28/2010
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Eckermann, Benjamin C., SATSANGI, Mohit, Chakravarthy, E.S. Kalyana, Shippen, Gregory B.
• Granted Patent: US 8,286,011 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted.

Claims

1. A method of waking a processor, connected to a network, from a sleep mode, comprising:

receiving a packet via a network connection;

classifying the packet in accordance with predetermined categories, said predetermined categories including interesting and not interesting;

storing the received packet in a memory if the packet is classified as an interesting packet;

initiating a receive timer upon receipt of a first interesting packet;

incrementing a counter upon receipt of an interesting packet;

asserting a wake-up interrupt when at least one of said counter reaches a predetermined count value and said timer expires, wherein said wake-up interrupt instructs the processor to transition from the sleep mode to an active mode.

2. The method of waking a processor of claim 1, wherein the memory comprises a double data rate (DDR) type memory.

3. The method of waking a processor of claim 2, wherein the DDR memory is maintained in a self-refresh mode until a packet is to be stored in the DDR memory.

4. The method of waking a processor of claim 2, wherein a clock signal to the DDR memory is gated at the pads of the DDR memory when there is no packet to store in the DDR memory.

5. The method of waking a processor of claim 1, wherein the received packet is discarded if the packet is classified as not interesting.

6. The method of waking a processor of claim 1, wherein said predetermined categories includes an immediate wake-up category, and wherein if the received packet is classified as an immediate wake-up packet then said wake-up interrupt is asserted.

7. The method of waking a processor of claim 6, wherein the classification of packets is user configurable.

8. The method of waking a processor of claim 6, wherein an initial receive timer value and the predetermined count value are programmable.

9. The method of waking a processor of claim 1, wherein the wake-up interrupt also is asserted if a transmit timer expires.

10. The method of waking a processor of claim 1, wherein the received packet is an Ethernet data packet and is classified as interesting if the packet is one of a ping, ICMP, and ARP.

11. A processor connectable to a network for receiving packets of data transmitted over the network, wherein the processor includes an active mode and a sleep mode, the processor comprising:

at least one processing unit that is powered down when the processor is in the sleep mode;

a network interface circuit connectable to the network for receiving and classifying the data packets transmitted over the network while the processor is in the sleep mode, wherein the packets are classified as at least one of an interesting packet and an uninteresting packet;

a memory coupled to the network interface circuit;

a receive timer coupled to the network interface circuit; and

a counter coupled to the network interface circuit;

wherein if the received packet is classified as an interesting packet then the interesting packet is stored in the memory, the receive timer is initiated, and the counter is incremented; and

wherein when at least one of the receive timer expires and the counter reaches a predetermined value then a wake-up interrupt is generated to wake up the at least one processing unit.

12. The processor of claim 11, wherein the memory is a double data rate (DDR) type memory.

13. The processor of claim 12, wherein the DDR memory is maintained in a self-refresh mode until a received packet is classified as an interesting packet and transmitted on a system bus to the DDR memory.

14. The processor of claim 12, wherein a clock signal to the DDR memory is gated at the pads of the DDR memory when there is no packet to store in the DDR memory.

15. The processor of claim 11, wherein the received packet is discarded if the packet is classified as not interesting.

16. The processor of claim 11, wherein a received packet also may be classified as an immediate wake-up packet in which case the wake up interrupt is generated to wake up the processor.

17. The processor of claim 11, wherein the receive timer is initiated only upon receipt of a first received packet that is classified as interesting.

18. The processor of claim 11, further comprising a transmit timer that is initiated when the processor enters the sleep mode and expires when the processor must transmit a data packet over the network, wherein upon expiration of the transmit timer the wake-up interrupt is generated.

19. A processor connectable to a network for receiving packets of data transmitted over the network, wherein the processor includes an active mode and a sleep mode, the processor comprising:

at least one processing unit that is powered down when the processor is in the sleep mode;

at least one cache coupled to the processing unit, wherein the cache is powered down when the processor is in the sleep mode;

a network interface circuit connectable to the network for receiving and classifying the data packets transmitted over the network while the processor is in the sleep mode, wherein the packets are classified as at least one of an interesting packet, an uninteresting packet, and an immediate wake up packet;

a memory coupled to the network interface circuit;

a receive timer coupled to the network interface circuit; and

a counter coupled to the network interface circuit,

wherein if the packet is classified as an uninteresting packet, the packet is discarded,

wherein if the packet is classified as an immediate wake-up packet a wake-up interrupt is asserted that causes the processor and the cache to transition from the sleep mode to the active mode,

wherein if the received packet is classified as an interesting packet then the interesting packet is stored in the memory, the receive timer is initiated, and the counter is incremented, and wherein when at least one of the receive timer expires and the counter reaches a predetermined value then a wake-up interrupt is generated to wake up the at least one processing unit and the cache.

20. The processor of claim 19, further comprising a transmit timer that is activated when the processor enters the sleep mode.