SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND DOPANT DIFFUSION RETARDING IMPLANTS AND RELATED METHODS

• US 20110215299A1
• Filed: 03/08/2011
• Published: 09/08/2011
• Est. Priority Date: 03/08/2010
• Status: Abandoned Application

• Current Assignee: Mears Technologies Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: RAO, KALIPATNAM
• Application Number:
  US13/042,826
• Publication Number:
  US 20110215299A1
• Time in Patent Office: Days
• US Class Current: 257/28
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, and a gate adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.

Claims

1. A semiconductor device comprising:

a substrate;

at least one MOSFET adjacent said substrate and comprising a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent said superlattice channel, and a gate adjacent said superlattice channel;

each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

a first dopant in at least one region adjacent at least one of said source and drain; and

a second dopant in the at least one region, said second dopant being different than said first dopant and reducing diffusion thereof.

2. The semiconductor device of claim 1 wherein the at least one region comprises a halo region adjacent said source and drain.

3. The semiconductor device of claim 1 wherein the at least one region comprises a source extension region adjacent said source and a drain extension region adjacent said drain.

4. The semiconductor device of claim 1 wherein the at least one region comprises a deep source region adjacent said source and a deep drain region adjacent said drain.

5. The semiconductor device of claim 1 wherein said first dopant comprises boron.

6. The semiconductor device of claim 1 wherein said second dopant comprises at least one of nitrogen, germanium, fluorine, aluminum, gallium, indium, and carbon.

7. The semiconductor device of claim 1 further comprising a contact layer on at least one of said source and drain.

8. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

10. The semiconductor device of claim 1 wherein said at least one non-semiconductor layer comprises oxygen.

11. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

12. The semiconductor device of claim 1 wherein said gate comprises an oxide layer overlying said superlattice channel and a gate electrode overlying said oxide layer.

13. The semiconductor device of claim 1 wherein said superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

14. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through said non-semiconductor layer therebetween.

15. A method for making a semiconductor device comprising:

forming at least one MOSFET adjacent a substrate, the at least one MOSFET comprising a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, a gate adjacent the superlattice channel, a first dopant in at least one region adjacent at least one of the source and drain, and a second dopant in the at least one region, the second dopant being different than the first dopant and reducing diffusion thereof;

each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

16. The method of claim 15 wherein the at least one region comprises a halo region adjacent the source and drain.

17. The method of claim 15 wherein the at least one region comprises a source extension region adjacent the source and a drain extension region adjacent the drain.

18. The method of claim 15 wherein the at least one region comprises a deep source region adjacent the source and a deep drain region adjacent the drain.

19. The method of claim 15 wherein the first dopant comprises boron.

20. The method of claim 15 wherein the second dopant comprises at least one of nitrogen, germanium, fluorine, aluminum, gallium, indium, and carbon.

21. The method of claim 15 wherein forming further comprises co-implanting the first and second dopants in the at least one region.

22. The method of claim 15 further comprising forming a contact layer on at least one of the source and drain regions.

23. The method of claim 15 wherein each base semiconductor portion comprises silicon.

24. The method of claim 15 wherein each base semiconductor portion comprises germanium.

25. The method of claim 15 wherein the at least one non-semiconductor layer comprises oxygen.

26. The method of claim 15 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

27. The method of claim 15 wherein the gate comprises an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

28. The method of claim 15 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

29. The method of claim 15 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.