SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110215319A1
• Filed: 05/10/2011
• Published: 09/08/2011
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun, SAKATA, Junichiro
• Granted Patent: US 9,136,390 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

Claims

1. An active matrix display device comprising:

a transistor which comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc;

an insulating layer comprising aluminum oxide over the oxide semiconductor layer; and

a pixel electrode in electrical contact with the oxide semiconductor layer.

9. The active matrix display device according to any one of claims 1-8 wherein the active matrix display device is a liquid crystal device.

10. The active matrix display device according to any one of claims 1-8 wherein the active matrix display device is a light emitting device.

12. The active matrix display device according to any one of claims 1-8, wherein the oxide semiconductor layer is amorphous.

13. The active matrix display device according to any one of claims 1-8, wherein the oxide semiconductor layer contains an insulating impurity.

2. An active matrix display device comprising:

a transistor which comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc;

a source electrode over the oxide semiconductor layer;

a drain electrode over the oxide semiconductor layer;

an insulating layer over the oxide semiconductor layer, the source electrode and the drain electrode; and

a pixel electrode in electrical contact with one of the source electrode and the drain electrode,

wherein one of the source electrode and the drain electrode has a portion which confronts the other of the source electrode and the drain electrode, and wherein the portion has a U-shape.

11. The active matrix display device according to claim 2 or 7, wherein the insulating layer comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and tantalum oxide.

3. An active matrix display device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a scan line driver circuit operationally connected to the pixel, the scan line driver circuit comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,

wherein a gate of the third transistor is electrically connected to the one of the source and the drain of the third transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and

wherein a gate of the eighth transistor is electrically connected to a gate of the fifth transistor,

wherein each of the transistor of the pixel, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc.

4. An active matrix display device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a driver circuit operationally connected to the pixel, the driver circuit comprising an inverter circuit, the inverter circuit comprising;

a first transistor; and

a second transistor,

wherein a source of the first transistor is electrically connected to a drain of the second transistor; and

wherein a gate of the first transistor is electrically connected to the source of the first transistor,

each of the transistor of the pixel, the first transistor and the second transistor comprising;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc.

5. An active matrix display device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a driver circuit operationally connected to the pixel, the driver circuit comprising an inverter circuit, the inverter circuit comprising;

a first transistor; and

a second transistor;

wherein a source of the first transistor is electrically connected to a drain of the second transistor; and

wherein a gate of the first transistor is electrically connected to a drain of the first transistor,

wherein each of the transistor of the pixel, the first transistor and the second transistor comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc.

6. An active matrix display device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a signal line driver circuit operationally connected to the pixel, the signal line driver circuit comprising;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,

wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,

wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,

wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,

wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,

wherein each of the transistor of the pixel, the first transistor, the second transistor, the third transistor and the fourth transistor comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc.

7. An active matrix display device comprising:

a first transistor wherein a gate of the first transistor is operationally connected to a scan line driver circuit;

a second transistor wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor;

an insulating layer over the first transistor and the second transistor; and

a pixel electrode electrically connected to one of a source and a drain of the second transistor,

wherein each of the first transistor and the second transistor comprises;

a gate electrode;

a gate insulating layer over the gate electrode; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc.

8. An active matrix display device comprising:

a capacitor wiring;

a first insulating layer over the capacitor wiring;

a transistor comprising;

a gate electrode;

a gate insulating layer over the gate electrode wherein the gate insulating layer is a part of the first insulating layer; and

an oxide semiconductor layer having a channel formation region over the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer comprising indium, tin and zinc;

a second insulating layer over the oxide semiconductor layer and the capacitor wiring; and

a pixel electrode in electrical contact with the oxide semiconductor layer,

wherein the pixel electrode overlaps the capacitor wiring with the first insulating layer and the second insulating layer interposed therebetween.