SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110215326A1
• Filed: 03/01/2011
• Published: 09/08/2011
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: IMAHAYASHI, Ryota, GODO, Hiromichi, KATO, Kiyoshi
• Granted Patent: US 8,680,679 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Claims

1. A semiconductor device comprising:

a source electrode and a drain electrode over a substrate;

a first insulating layer over the substrate, wherein the first insulating layer is in contact with a side surface of the source electrode and a side surface of the drain electrode;

an oxide semiconductor layer over the source electrode, the drain electrode, and the first insulating layer, wherein the oxide semiconductor layer is in contact with an upper surface of the first insulating layer, an upper surface of the source electrode, and an upper surface of the drain electrode;

a second insulating layer over the oxide semiconductor layer; and

a gate electrode over the second insulating layer.

2. The semiconductor device according to claim 1,

wherein the upper surface of the first insulating layer has a root-mean-square roughness of 1 nm or less.

3. The semiconductor device according to claim 1,

wherein the source electrode and the drain electrode are embedded by the first insulating layer and the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises gallium and zinc.

5. A semiconductor device comprising:

a first insulating layer over a substrate;

a source electrode and a drain electrode over the substrate;

an oxide semiconductor layer over and in contact with the first insulating layer, the source electrode, and the drain electrode;

a second insulating layer over the oxide semiconductor layer; and

a gate electrode over the second insulating layer,

wherein an upper surface of the first insulating layer, an upper surface of the source electrode, and an upper surface of the drain electrode exist coplanarly.

6. The semiconductor device according to claim 5,

wherein the upper surface of the first insulating layer has a root-mean-square roughness of 1 nm or less.

7. The semiconductor device according to claim 5,

wherein a difference in height between the upper surface of the first insulating layer and one of the upper surface of the source electrode and the upper surface of the drain electrode is less than 5 nm.

8. The semiconductor device according to claim 5,

wherein the oxide semiconductor layer comprises gallium and zinc.

9. A semiconductor device comprising:

a first transistor; and

a second transistor over the first transistor,

wherein the first transistor comprises;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer so as to overlap with the first channel formation region; and

a first source electrode and a first drain electrode electrically connected to the first channel formation region,

wherein the second transistor comprises;

an insulating layer;

a second source electrode and a second drain electrode wherein one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode;

an oxide semiconductor layer over the insulating layer, the second source electrode, and the second drain electrode;

a second gate insulating layer over the oxide semiconductor layer; and

a second gate electrode over the second gate insulating layer, and

wherein an upper surface of the insulating layer, an upper surface of the second source electrode, and an upper surface of the second drain electrode exist coplanarly.

10. The semiconductor device according to claim 9,

wherein the upper surface of the insulating layer has a root-mean-square roughness of 1 nm or less.

11. The semiconductor device according to claim 9,

wherein a difference in height between the upper surface of the second gate insulating layer and one of the upper surface of the second source electrode and the upper surface of the second drain electrode is less than 5 nm.

12. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer comprises gallium and zinc.

13. The semiconductor device according to claim 9,

wherein the first channel formation region comprises silicon.

14. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a source electrode and a drain electrode over a substrate;

forming an insulating layer so as to cover the source electrode and the drain electrode;

performing planarization treatment on the insulating layer so that an upper surface of the insulating layer, an upper surface of the source electrode, and an upper surface of the drain electrode exist coplanarly;

forming an oxide semiconductor layer over and in contact with the insulating layer, the source electrode, and the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer.

15. The method according to claim 14,

wherein the planarization treatment is performed so that the upper surface of the insulating layer has a root-mean-square roughness of 1 nm or less.

16. The method according to claim 14,

wherein the planarization treatment is performed so that a difference in height between the upper surface of the insulating layer and one of the upper surface of the source electrode and the upper surface of the drain electrode is less than 5 nm.

17. The method according to claim 14,

wherein the oxide semiconductor layer comprises gallium and zinc.

18. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a first transistor, the first transistor comprising;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer so as to overlap with the first channel formation region; and

a first source electrode and a first drain electrode electrically connected to the first channel formation region;

forming a second source electrode and a second drain electrode over the first source electrode and the first drain electrode so that one of the second source electrode and the second drain electrode is electrically connected to the first gate electrode;

forming an insulating layer so as to cover the second source electrode and the second drain electrode;

performing planarization treatment on the insulating layer so that an upper surface of the insulating layer, an upper surface of the second source electrode, and an upper surface of the second drain electrode exist coplanarly;

forming an oxide semiconductor layer over and in contact with the insulating layer, the second source electrode, and the second drain electrode;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer.

19. The method according to claim 18,

wherein the planarization treatment is performed so that the upper surface of the insulating layer has a root-mean-square roughness of 1 nm or less.

20. The method according to claim 18,

wherein the planarization treatment is performed so that a difference in height between the upper surface of the insulating layer and one of the upper surface of the second source electrode and the upper surface of the second drain electrode is less than 5 nm.

21. The method according to claim 18,

wherein the oxide semiconductor layer comprises gallium and zinc.

22. The method according to claim 18,

wherein the first channel formation region comprises silicon.