SEMICONDUCTOR DEVICES WITH HETEROJUNCTION BARRIER REGIONS AND METHODS OF FABRICATING SAME

• US 20110215338A1
• Filed: 03/08/2010
• Published: 09/08/2011
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun
• Granted Patent: US 9,117,739 B2
• Time in Patent Office: Days
• US Class Current: 257/73
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Claims

1. An electronic device, comprising:

a silicon carbide layer including an n-type drift region therein;

a contact forming a Schottky junction with the drift region; and

a p-type junction barrier region on the silicon carbide layer, the p-type junction barrier region including a p-type polysilicon region forming a P-N heterojunction with the drift region and the p-type junction barrier region being electrically connected to the contact.

2. The electronic device of claim 1, wherein the Schottky junction between the contact and the drift region is configured to conduct current at a lower forward voltage than the P-N heterojunction between the junction barrier region and the drift region.

3. The electronic device of claim 2, wherein the contact forms an ohmic contact to the p-type polysilicon region, and wherein the P-N heterojunction between the heterojunction barrier region and the drift region is configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the Schottky junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.

4. The electronic device of claim 1, further comprising:

a guard ring termination region at a surface of the silicon carbide layer laterally adjacent to the contact, wherein the guard ring termination region includes a second p-type polysilicon region on the drift region, the second p-type polysilicon region being electrically isolated from the contact under zero bias conditions.

5. The electronic device of claim 4, further comprising a junction termination region at the surface of the silicon carbide layer having a conductivity type opposite the conductivity type of the drift region, wherein the second p-type polysilicon region extends into the junction termination region.

6. The electronic device of claim 1, wherein the junction barrier region comprises a plurality of p-type polysilicon regions in the drift region and at least one p-type polysilicon minority injector pad in the drift region beneath the contact and electrically connected to the contact.

7. The electronic device of claim 6, wherein the minority injector pad has a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is larger than a surface area in the horizontal plane of one of the plurality of p-type polysilicon regions in the junction barrier region.

8. The electronic device of claim 6, wherein the minority carrier injector pad has a surface area in a horizontal plane parallel to a major surface of the silicon carbide layer that is at least about 10% of a surface area of the drift region in the horizontal plane below the contact.

9. The electronic device of claim 1, wherein the contact comprises a first contact, the device further comprising an n+silicon carbide contact layer on the drift region opposite the contact, and a second contact on the contact layer.

10. An electronic device, comprising:

a drift region having a first conductivity type;

a contact on the drift region and forming a junction with the drift region; and

a junction barrier region on the drift region, the junction barrier region having a second conductivity type opposite the first conductivity type and including a heterojunction barrier region on the drift region, wherein the heterojunction barrier region forms a P-N heterojunction with the drift region and is in electrical contact with the contact.

11. The electronic device of claim 10, wherein the junction between the contact and the drift region comprises a Schottky junction that is configured to conduct current at a lower forward voltage than the P-N heterojunction between the heterojunction barrier region and the drift region.

12. The electronic device of claim 10, wherein the contact forms an ohmic contact to the heterojunction barrier region, and wherein the P-N heterojunction between the heterojunction barrier region and the drift region is configured to begin to conduct majority carriers at a higher forward voltage than a turn on voltage of the junction and at a lower voltage at which the P-N heterojunction between the heterojunction barrier region and the drift region begins to inject minority carriers into the drift region.

13. The electronic device of claim 10, further comprising:

a guard ring termination region on the drift region and laterally adjacent to the junction, wherein the guard ring termination region includes a second heterojunction barrier region.

14. The electronic device of claim 10, wherein the heterojunction barrier region comprises a plurality of p-type polysilicon regions on the drift region and at least one p-type polysilicon minority injector pad on the drift region beneath the contact and electrically connected to the contact.

15. The electronic device of claim 14, wherein the minority carrier injection pad has a width that is greater than a width of the junction barrier region.

16. The electronic device of claim 14, wherein the minority injector pad has a horizontal surface area that is larger than a horizontal surface area of one of the plurality of p-type polysilicon regions in the junction barrier region.

17. The electronic device of claim 10, wherein the drift region comprises n-type silicon carbide and the heterojunction barrier region comprises p-type polysilicon.

18. The electronic device of claim 10, wherein the drift region comprises n-type silicon carbide and the heterojunction barrier region comprises p-type gallium nitride.

19. The electronic device of claim 10, further comprising:

a termination region at a surface of the drift region and defining an active region of the device within the termination region;

wherein a ratio of a surface area of the active region occupied by the heterojunction barrier regions to a total surface area of the active region is about 2% to about 40%.

20. The electronic device of claim 19, wherein the ratio of the surface area of the active region occupied by the heterojunction barrier regions to the total surface area of the active region is about 10% to about 30%.

21. The electronic device of claim 19, wherein the ratio of the surface area of the active region occupied by the heterojunction barrier regions to the total surface area of the active region is about 20% to about 30%.

22. A method of forming an electronic device, comprising:

providing a drift region having a first conductivity type;

providing a heterojunction barrier region on the drift region, the heterojunction barrier region comprising a material different from the drift region and having a conductivity type opposite the conductivity type of the drift region and forming a P-N heterojunction with the drift region; and

providing a contact on the drift region and on the heterojunction barrier region, the contact forming a Schottky junction with the drift region and forming an ohmic junction with the heterojunction barrier region.

23. The method of claim 22, wherein the drift region comprises n-type silicon carbide and the heterojunction barrier region comprises p-type polysilicon.

24. The method of claim 22, further comprising:

providing a guard ring termination region on the drift region laterally adjacent to the Schottky junction, wherein the guard ring termination region includes a second heterojunction barrier region on the drift region.

25. The method of claim 22, wherein providing the heterojunction barrier region comprises etching a recess in the drift region, depositing a polysilicon layer in the recess, doping the polysilicon layer to have a conductivity type opposite the conductivity type of the drift region, and patterning the polysilicon layer.

26. An electronic device, comprising:

a silicon carbide layer including a drift region having a first conductivity type;

a contact on a surface of the drift region and forming a junction with the drift region; and

a guard ring in contact with the surface of the silicon carbide layer adjacent to the junction, the guard ring having a conductivity type opposite the conductivity type of the drift region and including a material forming a heterojunction with the silicon carbide layer.

27. The electronic device of claim 26, wherein the guard ring comprises polysilicon.

28. The electronic device of claim 26, wherein the guard ring comprises gallium nitride.