PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION

• US 20110215376A1
• Filed: 03/08/2010
• Published: 09/08/2011
• Est. Priority Date: 03/08/2010
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Holt, Judson R., Tabakman, Keith H., Ontalus, Viorel C.
• Application Number:
  US12/719,312
• Publication Number:
  US 20110215376A1
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

Claims

1. A method of producing a transistor, said method comprising:

forming a base layer on a substrate;

forming a strain-producing layer on said base layer;

removing at least one portion of said strain-producing layer to create at least one opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;

growing a channel region in said opening of said strain-producing layer from said base layer;

forming a gate insulator on said channel region; and

forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator.

2. The method according to claim 1, further comprising forming shallow trench isolation regions either before forming said strain-producing conductive layer;

or

after forming said strain-producing conductive layer and before removing said portion of said strain-producing conductive layer;

or

after said growing of said channel region and before said forming of said gate conductor.

3. The method according to claim 1, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer, and said growing of said channel region comprising epitaxially growing said channel region.

4. The method according to claim 1, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer above a top level of adjacent shallow trench isolation regions,

said growing of said channel region comprising epitaxially growing said channel region above said top level of said strain-producing layer, and

said method further comprising polishing said strain-producing layer and said channel region until said strain-producing layer and said channel region are co-planar with said top level of said shallow trench isolation regions.

5. The method according to claim 1, said forming of said strain-producing conductive layer comprising forming a layer of one of SiGe and SiC.

6. A method of producing a transistor, said method comprising:

forming a base layer on a substrate;

forming a strain-producing layer on said base layer;

removing at least one portion of said strain-producing layer to create at least one opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;

growing a non-uniform channel region in said opening of said strain-producing layer from said base layer;

forming a gate insulator on said channel region; and

forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator.

7. The method according to claim 6, said growing of said non-uniform channel region comprising altering a doping concentration during an epitaxial growth of said non-uniform channel region to form a channel region having graded doping concentrations.

8. The method according to claim 6, said growing of said non-uniform channel region comprising epitaxially growing a first channel layer and epitaxially growing a second channel layer on said first channel layer.

9. The method according to claim 8, said first channel layer consisting of SiC and said second channel layer consisting of Si.

10. The method according to claim 6, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer.

11. The method according to claim 6, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer above a top level of adjacent shallow trench isolation regions,

said growing of said channel region comprising epitaxially growing said channel region above said top level of said strain-producing layer, and

said method further comprising polishing said strain-producing layer and said channel region until said strain-producing layer and said channel region are co-planar with said top level of said shallow trench isolation regions.

12. A method of producing a transistor, said method comprising:

forming a base layer on a substrate;

forming a strain-producing layer on said base layer;

removing at least one portion of said strain-producing layer to create at least one opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;

growing a first portion of a channel region in said opening of said strain-producing layer from said base layer;

growing second portion of said channel region on said first portion, said second portion comprising a different lattice constant than said first portion of said channel region;

forming a gate insulator on said second portion of said channel region; and

forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said first portion of said channel region, said second portion of said channel region, and said gate insulator.

13. The method according to claim 12, further comprising forming shallow trench isolation regions either before forming said strain-producing conductive layer;

or

after forming said strain-producing conductive layer and before removing said portion of said strain-producing conductive layer;

or

after said growing of said channel region and before said forming of said gate conductor.

14. The method according to claim 12, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer, and said growing of said channel region comprising epitaxially growing said channel region.

15. The method according to claim 12, said forming of said strain-producing layer comprising epitaxially growing said strain-producing layer above a top level of adjacent shallow trench isolation regions,

said growing of said channel region comprising epitaxially growing said channel region above said top level of said strain-producing layer, and

said method further comprising polishing said strain-producing layer and said channel region until said strain-producing layer and said channel region are co-planar with said top level of said shallow trench isolation regions.

16. The method according to claim 12, said forming of said strain-producing conductive layer comprising forming a layer of one of SiGe or SiC.

17. A transistor structure comprising:

a substrate;

a base layer on said substrate;

epitaxially grown source and drain stressor regions on said base layer;

an epitaxially grown channel region on said base layer between said source and drain stressor regions;

a gate insulator on said channel region; and

a gate conductor on said gate insulator,

said source and drain stressor regions being positioned partially below said gate conductor, and

said source and drain stressor regions having vertical sidewalls below said gate conductor.

18. The transistor structure according to claim 17, said channel region comprising doping concentrations.

19. The transistor structure according to claim 17, said channel region comprising a lower layer of SiC and an upper layer of Si.

20. The transistor structure according to claim 17, further comprising shallow trench isolation regions adjacent said source and drain stressor regions.

21. The transistor structure according to claim 17, said strain-producing layer comprising one of SiGe or SiC.

22. The transistor structure according to claim 17, said vertical sidewalls of said source and drain stressor regions being perpendicular to the plane of said gate insulator.