Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region
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Abstract
A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
55 Citations
44 Claims
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1-23. -23. (canceled)
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24. A vertically-conducting planar-gate field effect transistor comprising:
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a silicon region of a first conductivity type; a silicon-germanium layer extending over the silicon region; gate electrode laterally extending over but being insulated from the silicon-germanium layer; a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region; and source region of the first conductivity type extending in the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region. - View Dependent Claims (25)
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26-42. -42. (canceled)
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43. A method of forming a vertically-conducting planar-gate field effect transistor comprising:
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forming a silicon-germanium layer over a silicon region of a first conductivity type; forming a gate electrode laterally extending over but insulated from the silicon-germanium layer; forming a body region of a second conductivity type extending in the silicon-germanium layer and the silicon region; and forming a source region of the first conductivity type extending at least into the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region. - View Dependent Claims (44)
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Specification