Multichip semiconductor device, chip therefor and method of formation thereof

• US 20110215443A1
• Filed: 05/13/2011
• Published: 09/08/2011
• Est. Priority Date: 12/02/1996
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hayasaka, Nobuo, Okumura, Katsuya, Sasaki, Keiichi, Matsuo, Mie
• Granted Patent: US 8,283,755 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Claims

1-61. -61. (canceled)

62. A multichip semiconductor device including a plurality of chips stacked on each other, each of the chips having a semiconductor substrate on which circuit components are formed, wherein

two adjacent chips included in the plurality of chips are electrically connected to each other via a connecting substrate provided between the two adjacent chips, a through hole is formed in the semiconductor substrate, and a conductive plug formed in the through hole is connected to the connecting substrate.

63. The multichip semiconductor device according to claim 62, wherein

the connecting substrate has a conductive plug formed in the through hole, conductive plugs included in the two adjacent chips are electrically connected to the conductive plug in the connecting substrate and the connecting substrate has a heat radiation property higher than heat radiation properties of the plurality of chips.

64. The multichip semiconductor device according to claim 62, wherein the connecting substrate is made of a material having a heat radiation property higher than heat radiation properties of a material of the chips.

65. The multichip semiconductor device according to claim 62, wherein the connecting substrate comprises a connecting substrate body, and a thermal conductive member having a thermal conductivity higher than the connecting substrate body.

66. The multichip semiconductor device according to claim 65 wherein the thermal conductive member is a conductive plate formed in the connecting substrate body.

67. The multichip semiconductor device according to claim 65, wherein the thermal conductive member is a radiation fin provided on a surface of the connecting substrate body.

68. The multichip semiconductor device according to claim 63, wherein a multi-layer interconnection is formed in the connecting substrate.

69. The multichip semiconductor device according to claim 63, wherein the connecting substrate is made of an insulating material and a capacitor is formed within the connecting substrate, the capacitor including a first capacitor electrode formed of a power supply line, a second capacitor electrode formed of a ground line, and a capacitor insulating film formed of the connecting substrate.

70. The multichip semiconductor device according to claim 62, wherein the connecting substrate has a conductive plug formed in the through hole, conductive plugs included in the two adjacent chips are electrically connected to the conductive plug in the connecting substrate and a material of the connecting substrate has substantially the same thermal expansion coefficient as a material of the semiconductor substrate.

71. The multichip semiconductor device according to claim 70, wherein a difference between the thermal expansion coefficient of the material of the connecting substrate and the thermal expansion coefficient of the material of the semiconductor substrate is within ±

5.0×

10<sup>−

6</sup>.