SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE

• US 20110215478A1
• Filed: 03/03/2011
• Published: 09/08/2011
• Est. Priority Date: 03/04/2010
• Status: Abandoned Application

• Current Assignee: NEC Corporation, Renesas Electronics Corporation
• Original Assignee: NEC Corporation, Renesas Electronics Corporation
• Inventors: MURAI, Hideya, KIKUCHI, Katsumi, YAMAMICHI, Shintaro, KOMURO, Masahiro, KAWANO, Masaya, MORI, Kentaro, NAKASHIMA, Yoshiki
• Application Number:
  US13/040,021
• Publication Number:
  US 20110215478A1
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

In a wiring substrate containing a semiconductor element, the wiring substrate includes a supporting substrate; a semiconductor element provided on the supporting substrate; a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and upper surface-side wiring provided on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate; a first wiring-structure layer including first wiring and a first insulating layer alternately formed on the semiconductor substrate; and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

Claims

1. A wiring substrate containing a semiconductor element, the wiring substrate comprising:

a supporting substrate;

a semiconductor element provided on the supporting substrate;

a peripheral insulating layer provided on the supporting substrate and covering at least an outer circumferential side surface of the semiconductor element; and

upper surface-side wiring provided on the upper surface side of the wiring substrate,

the semiconductor element comprising;

a semiconductor substrate;

a first wiring-structure layer comprising first wiring and a first insulating layer alternately formed on the semiconductor substrate; and

a second wiring-structure layer comprising second wiring and a second insulating layer alternately formed on the first wiring-structure layer,

wherein the upper surface-side wiring comprises fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element, the fan-out wiring being electrically connected to the first wiring through the second wiring;

the thickness of the second wiring is greater than the thickness of the first wiring but less than the thickness of the upper surface-side wiring; and

the second insulating layer is formed of a resin material and greater in thickness than the first insulating layer.

2. The wiring substrate according to claim 1, wherein the supporting substrate is a metal plate.

3. The wiring substrate according to claim 1, wherein the second insulating layer is composed of a resin material without filler.

4. The wiring substrate according to claim 1, wherein the first wiring-structure layer includes, as the first insulating layer, an insulating layer composed of an inorganic insulating material.

5. The wiring substrate according to claim 1, wherein the first wiring-structure layer includes, as the first insulating layer, an insulating layer composed of a low-dielectric constant insulating material.

6. The wiring substrate according to claim 1, wherein the second wiring-structure layer includes, as the second insulating layer, an insulating layer having an elastic modulus lower than the elastic modulus of the first insulating layer.

7. The wiring substrate according to claim 1, wherein the second wiring has a thickness twice or more the thickness of the first wiring.

8. The wiring substrate according to claim 1, wherein the second insulating layer has a thickness twice or more the thickness of the first insulating layer.

9. The wiring substrate according to claim 1, wherein the second wiring is formed by a design rule different from the design rule of the first wiring and the design rule of the upper surface-side wiring, and the minimum wiring width and the minimum wiring pitch of the second wiring are greater than the minimum wiring width and the minimum wiring pitch of the first wiring, respectively, but less than the minimum wiring width and the minimum wiring pitch of the upper surface-side wiring.

10. The wiring substrate according to claim 1, wherein the first wiring-structure layer further includes, on the upper surface side thereof, a first connecting part connected to the second wiring, the second wiring-structure layer further includes, on the upper surface side thereof, a second connecting part conductive to the first connecting part and connected to the fan-out wiring, and the second connecting part is repositioned in a direction farther from a position of the first connecting part toward an outer edge side of the semiconductor element.

11. The wiring substrate according to claim 1, further comprising a protective insulating film covering the upper surface-side wiring,

wherein the protective insulating film includes an opening such that the wiring substrate is provided with an external terminal composed of an exposed portion of the upper surface-side wiring within the opening or of a conductive part provided in the opening.

12. The wiring substrate according to claim 1, further comprising a third wiring-structure layer including third wiring and a third insulating layer alternately formed on the semiconductor substrate, wherein the third wiring-structure layer includes the fan-out wiring as the third wiring on at least the lowermost layer side, and the fan-out wiring is electrically connected to an upper layer-side wiring provided in the third wiring-structure layer as the third wiring.

13. The wiring substrate according to claim 12, wherein the second insulating layer is composed of a resin material without filler, and the third wiring-structure layer includes, as the third insulating layer, an insulating layer composed of a filler-containing resin material.

14. The wiring substrate according to claim 12, wherein the thickness of the third wiring is greater than the thickness of the second wiring, and the thickness of the third insulating layer is greater than the thickness of the second insulating layer.

15. The wiring substrate according to claim 14, wherein the third wiring has a thickness twice or more the thickness of the second wiring.

16. The wiring substrate according to claim 14, wherein the third insulating layer has a thickness twice or more the thickness of the second insulating layer.

17. The wiring substrate according to claim 12, wherein the second wiring-structure layer includes as the second insulating layer an insulating layer having an elastic modulus higher than the elastic modulus of the third insulating layer.

18. The wiring substrate according to claim 12, further comprising an insulating layer on the uppermost layer side,

wherein the insulating layer includes an opening such that the wiring substrate is provided with an external terminal composed of an exposed portion of the third wiring within the opening or of a conductive part provided in the opening.

19. The wiring substrate according to claim 1, wherein the peripheral insulating layer includes a filler.

20. The wiring substrate according to claim 1, wherein the peripheral insulating layer contains a reinforcing material made of woven or nonwoven cloth.

21. The wiring substrate according to claim 1, wherein the peripheral insulating layer covers the outer circumferential side surface of the semiconductor element without covering the upper surface thereof, and the fan-out wiring is connected to a terminal on an upper surface of the semiconductor element.

22. The wiring substrate according to claim 1, wherein the peripheral insulating layer covers an upper surface and the outer circumferential side surface of the semiconductor element, and the fan-out wiring is provided on the peripheral insulating layer.

23. The wiring substrate according to claim 1, further comprising an element-side via penetrating the peripheral insulating layer, wherein the element-side via connects the third wiring and the supporting substrate.

24. The wiring substrate according to claim 1, wherein the semiconductor element further comprises, on the lower surface side of the semiconductor substrate, a fourth wiring-structure layer including a fourth insulating layer and fourth wiring.

25. The wiring substrate according to claim 24, wherein the semiconductor element further comprises an intra-element via penetrating the semiconductor substrate, and the intra-element via electrically connects the first wiring and the fourth wiring.

26. The wiring substrate according to claim 1, wherein the semiconductor element further comprises a reinforcing via penetrating the semiconductor substrate.