Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter

• US 20110216559A1
• Filed: 03/05/2010
• Published: 09/08/2011
• Est. Priority Date: 03/05/2010
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: So, Wai Kit (Victor), Kwong, Kwok Kuen, Ng, Chik Wai (David), Kwan, Hing Kit, Chang, Po Wah
• Granted Patent: US 8,300,431 B2
• Time in Patent Office: Days
• US Class Current: 363/21.13
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop

Abstract

A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.

Claims

1. A power converter comprising:

a transformer having a primary winding that receives an input voltage and outputs a drain voltage on a drain node, the transformer also having a secondary winding that outputs a secondary current that is induced by mutual induction from changes in a primary current through the primary winding;

a switch that receives the primary current from the transformer at the drain node, and is controlled by a gate voltage to switch the primary current to a primary-sensing node, wherein the switch is a metal-oxide-semiconductor field-effect transistor (MOSFET);

a primary sensing resistor coupled to the primary-sensing node and generating a primary-sensing voltage on the primary-sensing node when the switch connects the primary current to the primary sensing resistor;

a bistable latch that generates a switch signal that controls the gate voltage to the switch;

a reset comparator that receives the primary-sensing voltage and receives a feedback voltage, and generates a reset signal to the bistable latch when the primary-sensing voltage crosses the feedback voltage;

wherein the reset signal resets the bistable latch to deactivate the switch signal and drive the gate voltage to a disabling voltage that causes the switch to isolate the transformer from the primary sensing resistor;

a multiplier that receives the switch signal from the bistable latch and receives the feedback voltage, the multiplier multiplying the feedback voltage by an off duty cycle indicated by a ratio of a time that the switch signal is inactive to a period of the switch signal to generate a filtered voltage;

an error amp that receives the filtered voltage from the multiplier and receives a reference voltage, the error amp comparing the filtered voltage to the reference voltage to generate the feedback voltage; and

a set signal that sets the bistable latch to activate the switch signal and drive the gate voltage to an enabling voltage that causes the switch to conduct the primary current from the transformer to the primary sensing resistor,

whereby the primary current is switched to control the secondary current.

2. The power converter of claim 1 wherein the multiplier comprises:

a level-shift inverter that receives the feedback voltage and the switch signal and passes the feedback voltage to a filter input when the switch signal is deactivated, and passes a zero signal to the filter input when the switch signal is activated;

a low pass filter connected between the filter input and a filtered input to the error amp, the low pass filter generating the filtered voltage on the filtered input to the error amp from the filter input.

3. The power converter of claim 2 wherein the low pass filter comprises:

a series resistor between the filter input and the filtered input to the error amp;

a filter capacitor coupled to the filtered input to the error amp, the filter capacitor being charged by the level-shift inverter passing the feedback voltage when the switch signal is deactivated.

4. The power converter of claim 3 wherein the level-shift inverter comprises:

a p-channel transistor receiving the switch signal on a gate and connecting the feedback voltage to the filter input when the switch signal is inactive;

an n-channel pull-down transistor receiving the switch signal on a gate and connecting the filter input to a ground when the switch signal is active;

an n-channel connecting transistor receiving an inverse of the switch signal on a gate and connecting the feedback voltage to the filter input when the switch signal is inactive.

5. The power converter of claim 2 further comprising:

a third winding of the transformer that outputs an auxiliary current on an auxiliary node, the auxiliary current being induced by mutual induction from changes in the primary current through the primary winding;

a set comparator that connects to the auxiliary node and to a ground, the set comparator generating the set signal to the bistable latch when an auxiliary voltage on the auxiliary node crosses the ground;

wherein the set signal sets the bistable latch to activate the switch signal and drive the gate voltage to an enabling voltage that causes the switch to conduct the primary current from the transformer to the primary sensing resistor,

whereby the bistable latch generates the switch signal as a Quasi-Resonant (QR) control signal.

6. The power converter of claim 5 wherein the Quasi-Resonant (QR) control signal has reduced Electro-Magnetic Interference (EMI) compared with a Pulse-Width-Modulation (PWM) control signal.

7. The power converter of claim 5 further comprising:

a secondary diode coupled between the transformer and an output node, the secondary diode carrying the secondary current from the transformer.

8. The power converter of claim 2 wherein an average of the secondary current, IS_ave, is related to the reference voltage Vref applied to the error amp, a resistance value RS of the primary sensing resistor, and a number of turns in the primary winding Np and a number of turns in the secondary winding Ns of the transformer by an equation:

IS_—

ave=1/2*Np/Ns*Vref/RS.

9. The power converter of claim 5 further comprising:

an auxiliary diode coupled between the transformer and a VCC power supply node, the auxiliary diode carrying the auxiliary current from the transformer;

wherein the VCC power supply node powers the bistable latch, the reset comparator, the error amp, and the set comparator.

10. The power converter of claim 9 further comprising:

a connection to an alternating-current (AC) power supply having an AC+ and an AC−

output;

a full-wave rectifier comprising;

a first diode connected between the AC−

output and the input voltage and forward biased from the AC−

output and the input voltage;

a second diode connected between the AC+ output and the input voltage and forward biased from the AC+ output and the input voltage;

a third diode connected between the AC−

output and a ground and forward biased from the ground to the AC−

output;

a fourth diode connected between the AC+ output and the ground and forward biased from the ground to the AC+ output;

a power capacitor coupled between the input voltage and the ground.

11. The power converter of claim 5 wherein the bistable latch is a Set-Reset SR latch having a set input and a reset input;

further comprising;

a switch buffer that receives the switch signal from the bistable latch and generates the gate voltage to the switch.

12. The power converter of claim 2 wherein the set signal is generated by an oscillator that generates a periodic signal,

wherein the bistable latch is set by the periodic signal from the oscillator for Pulse-Width-Modulation (PWM) control of the switch.

13. A multiplier-based power converter comprising:

a rectified input voltage generated from a diode rectifier on an input node;

a transformer having a primary winding for carrying a primary current between the rectified input voltage on the input node and a drain node, and having a secondary winding for carrying a secondary current for output on a secondary node, wherein the secondary current is induced by mutual inductance from changes in the primary current;

a secondary diode connected between the secondary node and an output node;

a switch transistor having a drain connected to the drain node, a source connected to a primary-sensing node, and a gate connected to a gate node;

a primary sensing resistor connected between the primary-sensing node and a ground;

a first comparator receiving a primary sensing voltage from the primary-sensing node and receiving a feedback voltage, for generating a reset signal when the primary sensing voltage rises above the feedback voltage;

a latch that is reset by the reset signal from the first comparator and set by a set signal, the latch generating a switch signal that controls a gate voltage on the gate node of the switch transistor;

a level-shift inverter that receives the switch signal from the latch and the feedback voltage, the level-shift inverter driving a filter input node with the feedback voltage when the switch signal causes the gate voltage to disable the switch transistor;

a series resistor coupled between the filter input node and a filter output node;

a filter capacitor coupled between the filter output node and a fixed voltage;

an error amplifier receiving the filter output node and a reference voltage as inputs, and amplifies a voltage difference between the reference voltage and a filtered voltage on the filter output node to generate the feedback voltage,

wherein the primary sensing voltage is generated by the primary current flowing through the primary sensing resistor, the primary sensing voltage resetting the latch and disabling the switch transistor to block the primary current when the primary sensing voltage rises to the feedback voltage,

whereby the level-shift inverter, series resistor, and filter capacitor act as a multiplier to

multiply an off duty cycle of the switch transistor by the feedback voltage.

14. The multiplier-based power converter of claim 13 wherein the latch is a Set-Reset latch;

further comprising;

a switch buffer receiving the switch signal and generating the gate voltage; and

a first leading-edge-blanking circuit, coupled to the first comparator, for blocking glitches on the primary sensing voltage from generating the reset signal.

15. The multiplier-based power converter of claim 13 further comprising:

a third winding in the transformer that carries an auxiliary current to an auxiliary node;

wherein the auxiliary current is induced by mutual inductance from changes in the primary current;

an auxiliary diode connected between the auxiliary node and an internal power-supply node;

an internal power-supply capacitor coupled between the internal power-supply node and the ground; and

a second comparator that receives an auxiliary voltage from the auxiliary node and a fixed voltage, the second comparator generating the set signal by comparing the auxiliary voltage to the fixed voltage.

16. The multiplier-based power converter of claim 15 wherein the set signal and the reset signal control the latch to generate the switch signal using a Quasi-Resonant (QR) control;

wherein the fixed voltage is the ground.

17. The multiplier-based power converter of claim 13 further comprising:

an oscillator for generating a periodic signal;

an edge detector for generating the set signal to the latch from the periodic signal,

wherein the set signal and the reset signal control the latch to generate the switch signal using a Pulse-Width-Modulation (PWM) control.

18. The multiplier-based power converter of claim 13 wherein an average of the secondary current, IS_ave, is related to the reference voltage Vref applied to the error amplifier, a resistance value RS of the primary sensing resistor, and a number of turns in the primary winding Np and a number of turns in the secondary winding Ns of the transformer by an ideal equation:

IS_—

ave=1/2*Np/Ns*Vref/RS,

wherein a measured average secondary current is within 10 percent of a value calculated by the ideal equation.

19. A hybrid power converter comprising:

a rectified input voltage generated from a diode rectifier on an input node;

a transformer having a primary winding for carrying a primary current between the rectified input voltage on the input node and a drain node, and having a secondary winding for carrying a secondary current for output on a secondary node, wherein the secondary current is induced by mutual inductance from changes in the primary current;

a secondary diode connected between the secondary node and an output node;

a switch transistor having a drain connected to the drain node, a source connected to a primary-sensing node, and a gate connected to a gate node;

a primary sensing resistor connected between the primary-sensing node and a ground;

a first comparator receiving a primary sensing voltage from the primary-sensing node and receiving a feedback voltage, for generating a reset signal when the primary sensing voltage rises above the feedback voltage;

a latch that is reset by the reset signal from the first comparator and set by a set signal, the latch generating a switch signal that controls a gate voltage on the gate node of the switch transistor;

an oscillator for generating a periodic signal;

an edge detector for generating the set signal to the latch from the periodic signal,

wherein the set signal and the reset signal control the latch to generate the switch signal using a Pulse-Width-Modulation (PWM) control;

a middle latch that is set by the reset signal from the first comparator and reset by a middle reset signal, the middle latch generating a middle signal;

a level-shift inverter that receives the middle signal from the middle latch and receives the feedback voltage, the level-shift inverter driving a filter input node with the feedback voltage when the middle signal is activated;

a series resistor coupled between the filter input node and a filter output node;

a filter capacitor coupled between the filter output node and a fixed voltage; and

an error amplifier receiving the filter output node and a reference voltage as inputs, and amplifies a voltage difference between the reference voltage and a filtered voltage on the filter output node to generate the feedback voltage,

wherein the primary sensing voltage is generated by the primary current flowing through the primary sensing resistor, the primary sensing voltage resetting the latch and disabling the switch transistor to block the primary current when the primary sensing voltage rises to the feedback voltage,

whereby the level-shift inverter, series resistor, and filter capacitor act as a multiplier to

multiply an off duty cycle of the switch transistor by the feedback voltage.

20. The hybrid power converter of claim 19 further comprising:

a third winding in the transformer that carries an auxiliary current to an auxiliary node;

wherein the auxiliary current is induced by mutual inductance from changes in the primary current;

an auxiliary diode connected between the auxiliary node and an internal power-supply node;

an internal power-supply capacitor coupled between the internal power-supply node and the ground; and

a second comparator that receives an auxiliary voltage from the auxiliary node and a fixed voltage, the second comparator generating the middle reset signal by comparing the auxiliary voltage to the fixed voltage.