SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor memory device comprising:
- a first memory cell including a first transistor, a second transistor, and a capacitor;
a second memory cell including a third transistor;
a first line;
a second line;
a third line;
a fourth line; and
a fifth line,wherein a gate of the first transistor is electrically connected to the first line,wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line,wherein the other of the source and the drain of the first transistor is electrically connected to the third line,wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, andwherein the other of the source and the drain of the second transistor is electrically connected to the fifth line.
1 Assignment
0 Petitions
Accused Products
Abstract
A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line.
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Citations
21 Claims
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1. A semiconductor memory device comprising:
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a first memory cell including a first transistor, a second transistor, and a capacitor; a second memory cell including a third transistor; a first line; a second line; a third line; a fourth line; and a fifth line, wherein a gate of the first transistor is electrically connected to the first line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor, wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line, wherein the other of the source and the drain of the first transistor is electrically connected to the third line, wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and wherein the other of the source and the drain of the second transistor is electrically connected to the fifth line. - View Dependent Claims (2, 3, 5, 6, 7)
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4. The semiconductor memory device according to claim
wherein one of a source and a drain of the third transistor is electrically connected to the third line.
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8. A semiconductor memory device comprising:
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a first memory cell including a first transistor, a second transistor, and a capacitor; a second memory cell including a third transistor; a first line; a second line; a third line; and a fourth line, wherein a gate of the first transistor is electrically connected to the first line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor, wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line, wherein the other of the source and the drain of the first transistor is electrically connected to the third line, wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and wherein the other of the source and the drain of the second transistor is electrically connected to the third line. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor memory device comprising:
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a first memory cell including a first transistor, a second transistor, and a first capacitor; a second memory cell including a third transistor; a third memory cell including a fourth transistor, a fifth transistor, and a second capacitor; a first line; a second line; a third line; and a fourth line, wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to the first line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the first capacitor, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the fifth transistor and a first electrode of the second capacitor, wherein a second electrode of the first capacitor, a second electrode of the second capacitor, and a gate of the third transistor are electrically connected to the second line, wherein the other of the source and the drain of the first transistor is electrically connected to the third line, wherein one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor are electrically connected to the fourth line, and wherein the other of the source and the drain of the second transistor is electrically connected to the third line. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification